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mb90340e series f 2 mc-16lx 16-bit microcontroller datasheet cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04498 rev. *a revised may 4, 2016 the mb90340e series with up to 2 full-can interfaces is espec ially designed for automotive and other industrial applications. i ts main feature are the on-board can interfaces, which conform to v2 .0 part a and part b, while supporting a very flexible message buffer scheme and so offering more functions than a normal full can approach. the power to the mcu core (3 v) is supplied by a built-in regu lator circuit, giving these microcontrollers superior performance in terms of power consumption and tolerance to emi. features cpu ? instruction system best suited to controller - wide choice of data types (bit, byte, word, and long word) - wide choice of addressing modes (23 types) - enhanced functionality with signed multiply and divide instructions and the reti instruction - enhanced high-precision com puting with 32-bit accumulator ? instruction system compatible with high-level language (c language) and multitask - employing system stack pointer - various enhanced pointer indirect instructions - barrel shift instructions ? increased processing speed - 4-byte instruction queue serial interface ? lin-uart : 4 channels - equipped with full-duplex double buffer - clock-asynchronous or clock-syn chronous serial transmission is available ? i 2 c interface : 2 channels (only for devices with a c suffix in the part number) - up to 400 kbps transfer rate interrupt controller ? powerful 8-level, 34-condition interrupt feature ? up to 16 external interrupts are supported ? automatic data transfer function independent of cpu - expanded intelligent i/o service function (ei 2 os) : up to 16 channels i/o ports ? general-purpose input/output port (cmos output) - 80 ports (for devices without an s suffix in the part number - i.e. devices that support the sub clock) - 82 ports (for devices with an s suffix in the part number - i.e. devices that do not support the sub clock) 8/10-bit a/d converter ? 16 channels (only for devices without a c suffix in the part number) ? 24 channels (only for devices with a c suffix in the part number) ? resolution is selectable between 8-bit and 10-bit. ? activation by external trigger input is allowed. ? conversion time : 3 ? s (at 24 mhz machine clock, including sampling time) address match detection (program patch) func- tion ? detects address matches against 6 address pointers timer ? time-base timer, watch timer, watchdog timer : 1 channel ? 8/16-bit ppg timer : 8-bit ? 16 channels, or 16-bit ? 8 channels ? 16-bit reload timer : 4 channels ? 16-bit input/output timer - 16-bit free-run timer : 2 channels (frt0 : icu 0/1/2/3, ocu 0/1/2/ 3, frt1 : icu 4/5/6/7, ocu 4/ 5/6/7) - 16-bit input captur e: (icu): 8 channels - 16-bit output comp are: (ocu): 8 channels full-can controller ? up to 2 channels ? compliant with ver2.0a and ver2.0b can specifications ? 16 built-in message buffers ? can wake-up function low power consumption (standby) mode ? sleep mode (a mode that halts cpu operating clock) ? timebase timer mode (a mode where only the oscillation clock, sub clock, timebase timer and watch timer operate) ? watch mode (a mode that operates sub clock and watch timer only) ? stop mode (a mode that stops oscillation clock and sub clock) ? cpu intermittent operation mode clock modulation circuit technology ? cmos technology
document number: 002-04498 rev. *a page 2 of 92 mb90340e series contents product lineup ................................................................ 3 pin assignments .............................................................. 6 pin description ............................................................... 12 i/o circuit type ............................................................... 19 handling devices ............................................................ 23 block diagrams .............................................................. 26 memory map .................................................................... 28 i/o map ............................................................................ 30 can controllers .............................................................. 41 interrupt factors, interrupt vectors, interrupt control register .............................................. 48 electrical characteristics ............................................... 50 absolute maximum ratings .... ................................... 50 recommended operating conditions ....................... 52 dc characteristics .................................................... 53 ac characteristics ..................................................... 55 clock timing .............................................................. 55 reset standby input .................................................. 58 power on reset ........................................................ 59 clock output timing .................................................. 59 bus timing (read) .................................................... 60 bus timing (write) ..................................................... 61 ready input timing ............... .............. .............. ........ 62 hold timing ............................................................... 63 lin-uart0/1/2/3 ....................................................... 64 trigger input timing ........... ....................................... 69 timer related resource inpu t timing ....................... 70 timer related resource output timing .................... 70 i2c timing ................................................................. 71 a/d converter ............................................................ 72 definition of a/d converter terms ........................... 73 notes on a/d converter sect ion ............................... 74 flash memory program/erase characteristics ......... 76 example characteristics ......... ....................................... 77 ordering information ...................................................... 86 package dimensions ...................................................... 89 major changes ................................................................ 91
document number: 002-04498 rev. *a page 3 of 92 mb90340e series 1. product lineup (continued) part number parameter mb90v340e-101, mb90v340e-102 mb90f342e(s), mb90f342ce(s), mb90f345e(s), mb90f345ce(s), mb90f346e(s), mb90f346ce(s), mb90f347e(s), mb90f347ce(s), mb90f349e(s), mb90f349ce(s) mb90341e(s), mb90341ce(s), mb90342e(s), mb90342ce(s), mb90346e(s), mb90346ce(s), mb90347e(s), mb90347ce(s), mb90348e(s), mb90348ce(s), mb90349e(s), mb90349ce(s) type evaluation products flash me mory products mask rom products cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier ( ? 1, ? 2, ? 3, ? 4, ? 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (4 mhz osc. pll ? 6) rom external 512 kbytes : mb90f345e(s), mb90f345ce(s) 256 kbytes : mb90f342e(s), mb90f342ce(s), mb90f349e(s), mb90f349ce(s) 128 kbytes : mb90f347e(s), mb90f347ce(s) 64 kbytes : mb90f346e(s), mb90f346ce(s) 256 kbytes : mb90342e(s), mb90342ce(s), mb90349e(s), mb90349ce(s) 128 kbytes : mb90341e(s), mb90341ce(s), mb90347e(s), mb90347ce(s), mb90348e(s), mb90348ce(s) 64 kbytes : mb90346e(s), mb90346ce(s) ram 30 kbytes 20 kbytes : mb90f345e(s), mb90f345ce(s) 16 kbytes : mb90f342e(s), mb90f342ce(s), mb90f349e(s), mb90f349ce(s) 6 kbytes : mb90f347e(s), mb90f347ce(s) 2 kbytes : mb90f346e(s), mb90f346ce(s) 16 kbytes : mb90341e(s), mb90341ce(s), mb90342e(s), mb90342ce(s), mb90348e(s), mb90348ce(s), mb90349e(s), mb90349ce(s) 6 kbytes : mb90347e(s), mb90347ce(s) 2 kbytes : mb90346e(s), mb90346ce(s) emulator-specific power supply* yes ? technology 0.35 ? m cmos with regulator for built-in power supply 0.35 ? m cmos with built-in power supply regulator ? flash memory with charge pump for programming voltage operating voltage range 5 v ? 10 ? 3.5 v to 5.5 v : when normal operating (not using a/d converter) 4.0 v to 5.5 v : when using the a/d converter/flash programming 4.5 v to 5.5 v : when using the external bus temperature range ?? 40c to ? 105c package pga-299 qfp-100, lqfp-100 lin-uart 5 channels 4 channels wide range of baud rate settings using a dedicated baud rate generator (reload timer) special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 2 channels devices with a c suffix in the part number : 2 channels devices without a c suffix in the part number : ?
document number: 002-04498 rev. *a page 4 of 92 mb90340e series part number parameter mb90v340e-101, mb90v340e-102 mb90f342e(s), mb90f342ce(s), mb90f345e(s), mb90f345ce(s), mb90f346e(s), mb90f346ce(s), mb90f347e(s), mb90f347ce(s), mb90f349e(s), mb90f349ce(s) mb90341e(s), mb90341ce(s), mb90342e(s), mb90342ce(s), mb90346e(s), mb90346ce(s), mb90347e(s), mb90347ce(s), mb90348e(s), mb90348ce(s), mb90349e(s), mb90349ce(s) a/d converter 24 input channels devices with a c suffix in the part number : 24 channels devices without a c suffix in the part number : 16 channels 10-bit or 8-bit resolution conversion time : min 3 ? s include sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys ? machine clock frequency) supports external event count function 16-bit free-run timer (2 channels) generates an interrupt signal on overflow supports timer clear when the output compare finds a match operation clock fr eq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys ? machine clock freq.) free-run timer 0 (clock input frck0) corresponds to icu 0/1/2/3, ocu 0/1/2/3 free-run timer 1 (clock input frck1) corresponds to icu 4/5/6/7, ocu 4/5/6/7 16-bit output compare (8 channels) generates an interrupt signal when one of the 16-bit free-run timer matches the output compare register a pair of compare registers can be used to generate an output signal. 16-bit input capture (8 channels) captures the value of the 16-bit free-run timer and generat es an interrupt when triggered by a pin input (rising edge, falling edge, or both rising and falling edges). 8/16-bit programmable pulse generator 8 channels (16-bit) /16 channels (8-bit) sixteen 8-bit reload counters sixteen 8-bit reload registers for l pulse width sixteen 8-bit reload registers for h pulse width supports 8-bit and 16-bit operation modes a pair of 8-bit reload counters can be co nfigured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter operating clock fr eq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 ? s@fosc ? 4 mhz (fsys ? machine clock frequency, fosc ? oscillation cl ock frequency) can interface 3 channels 2 channels : mb90f342e(s), mb90f342ce(s), mb90f345e(s), mb90f345ce(s) 1 channel : mb90f346e(s), mb90f346ce(s), mb90f347e(s), mb90f347ce(s), mb90f349e(s), mb90f349ce(s) 2 channels : mb90341e(s), mb90341ce(s), mb90342e(s), mb90342ce(s) 1 channel : mb90346e(s), mb90346ce(s), mb90347e(s), mb90347ce(s), mb90348e(s), mb90348ce(s), mb90349e(s), mb90349ce(s) conforms to can specification version 2.0 part a and b automatic re-transmission in case of error automatic transmission in response to remote frames prioritized 16 message buffers for data and id?s supports multiple messages flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps
document number: 002-04498 rev. *a page 5 of 92 mb90340e series (continued) * : it is setting of jumper switch (tool vcc) when emulator (mb2147-01-e) is used. please refer to the emulator operation manual for details. part number parameter mb90v340e-101, mb90v340e-102 mb90f342e(s), mb90f342ce(s), mb90f345e(s), mb90f345ce(s), mb90f346e(s), mb90f346ce(s), mb90f347e(s), mb90f347ce(s), mb90f349e(s), mb90f349ce(s) mb90341e(s), mb90341ce(s), mb90342e(s), mb90342ce(s), mb90346e(s), mb90346ce(s), mb90347e(s), mb90347ce(s), mb90348e(s), mb90348ce(s), mb90349e(s), mb90349ce(s) external interrupt (16 channels) can be used rising edge, falling edge, starting up by h/l level input, external interrupt, expanded intelligent i/o services (ei 2 os) and dma d/a converter 2 channels ? sub clock (maximum 100 khz) only for mb90v340e-102 devices with sub clock : devices without an s suffix in the part number devices without sub clock : devices with an s suffix in the part number i/o ports virtually all external pins can be used as general purpose i/o port all ports are push-pull outputs bit-wise settable as input/output or peripheral signal can be configured 8 as cmos schmitt trigger/ automotive inputs (in blocks of 8 pins) ttl input level settable for external bus (32-pin only for external bus) flash memory ? supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles : 10000 cycles data retention time : 20 years boot block configuration erase can be performed on each block block protection with external programming voltage flash security feature for protecting the content of the flash (except for mb90f346e(s) and mb90f346ce (s) )
document number: 002-04498 rev. *a page 6 of 92 mb90340e series 2. pin assignments ? mb90341e(s), mb90342e(s), mb90f342e(s), mb90f345e(s), mb90346e(s), mb90f346e(s), mb90347e(s), mb90f347e(s), mb9034 8e(s), mb90349e(s), mb90f349e(s) (continued) (top view) (fpt-100p-m06) * : x0a, x1a : devices without an s suffix in the part number p40, p41 : devices with an s suffix in the part number 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p75/int5 p74/int4 p73/int3 p72/int2 p71/int1 p70/int0 vss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p63/an3/ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2(3) p60/an0/ppg0(1) avss avrl avrh avcc p57/an15 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 pa1/tx0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/int7 p76/int6 md0 md1 md2 p24/a20/in0 p25/a21/in1 p26/a22/in2 p27/a23/in3 p30/ale/in4 p32/wrlx/wrx/int10r p34/hrq/out4 p56/an14 p55/an13 p54/an12/tot3 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47 p46 p45/frck1 p44/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a * p40/x0a * p37/clk/out7 p36/rdy/out6 qfp - 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 rst p31/rd/in5 p33/wrh p35/hak/out5
document number: 002-04498 rev. *a page 7 of 92 mb90340e series (continued) (top view) (fpt-100p-m20) * : x0a, x1a : devices without an s suffix in the part number p40, p4 : devices with an s suffix in the part number 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p00/ad00/int8 pa1/tx0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/int7 p76/int6 md0 p26/a22/in2 p27/a23/in3 p30/ale/in4 p32/wrl/wr/int10r p34/hrq/out4 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47 p46 p45/frck1 p44/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a* p40/x0a* p37/clk/out7 p36/rdy/out6 99 p24/a20/in0 100 p25/a21/in1 28 p56/an14 27 p55/an13 26 p54/an12/tot3 49 md2 50 md1 78 p03/ad03/int11 77 p02/ad02/int10 76 p01/ad01/int9 lqfp - 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 12345678910111213141516171819202122232425 p75/int5 p74/int4 p73/int3 p72/int2 p71/int1 p70/int0 vss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p63/an3/ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2(3) p60/an0/ppg0(1) avss avrl avrh avcc p57/an15 rst p31/rd/in5 p33/wrh p35/hak/out5
document number: 002-04498 rev. *a page 8 of 92 mb90340e series ? mb90341ce(s), mb90342ce(s), mb90f342ce(s), mb90f345 ce(s), mb90346ce(s), mb90f346ce(s), mb90347ce(s), mb90f347ce(s), mb90348ce(s), mb90349ce(s), mb90f349ce(s) (continued) (top view) (fpt-100p-m06) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p75/an21/int5 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 pa1/tx0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/an23/int7 p76/an22/int6 md0 md1 md2 p24/a20/in0 p25/a21/in1 p26/a22/in2 p27/a23/in3 p30/ale/in4 p34/hrq/out4 p56/an14 p55/an13 p54/an12/tot3 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47/scl1 p46/sda1 p45/scl0/frck1 p44/sda0/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a* p40/x0a* p37/clk/out7 p36/rdy/out6 qfp - 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 123456789101112131415161718192021222324252627282930 p74/an20/int4 p73/an19/int3 p72/an18/int2 p71/an17/int1 p70/an16/int0 p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p61/an1/ppg2(3) avss p57/an15 avcc p60/an0/ppg0(1) avrl avrh vss p62/an2/ppg4(5) p63/an3/ppg6(7) rst p31/rd/in5 p33/wrh p35/hak/out5 p32/wrl/wr/int10r * : x0a, x1a : devices without an s suffix in the part number p40, p41 : devices with an s suffix in the part number
document number: 002-04498 rev. *a page 9 of 92 mb90340e series (continued) (top view) (fpt-100p-m20) 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p00/ad00/int8 pa1/tx0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/an23/int7 p76/an22/int6 md0 p26/a22/in2 p27/a23/in3 p30/ale/in4 p34/hrq/out4 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47/scl1 p46/sda1 p45/scl0/frck1 p44/sda0/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a* p40/x0a* p37/clk/out7 p36/rdy/out6 99 p24/a20/in0 100 p25/a21/in1 28 p56/an14 27 p55/an13 26 p54/an12/tot3 49 md2 50 md1 78 p03/ad03/int11 77 p02/ad02/int10 76 p01/ad01/int9 lqfp - 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p75/an21/int5 p74/an20/int4 p73/an19/int3 p72/an18/int2 p71/an17/int1 p70/an16/int0 vss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p63/an3/ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2(3) p60/an0/ppg0(1) avss avrl avrh avcc p57/an15 rst p31/rd/in5 p33/wrh p35/hak/out5 p32/wrl/wr/int10r * : x0a, x1a : devices without an s suffix in the part number p40, p41 : devices with an s suffix in the part number
document number: 002-04498 rev. *a page 10 of 92 mb90340e series ? mb90v340e-101/mb90v340e-102 this pin assignment is for using mb90v34 0e-101/102 via probecable as mb90340e. (continued) (top view) (fpt-100p-m06) * : x0a, x1a : mb90v340e-102 p40, p41 : mb90v340e-101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15/sck4 p16/ad14/sot4 p15/ad13/sin4 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 30 18 p75/an21/int5 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 pa1/tx0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/an23/int7 p76/an22/int6 rst md0 md1 md2 p24/a20/in0 p25/a21/in1 p26/a22/in2 p27/a23/in3 p30/ale/in4 p31/rd/in5 p32/wrl/wr/rx2/int10r p33/wrh/tx2 p34/hrq/out4 p35/hak/out5 p56/an14/da00 p55/an13 p54/an12/tot3 p53/an11/tin 3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47/scl1 p46/sda1 p45/scl0/frck1 p44/sda0/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a * p40/x0a * p37/clk/out7 p36/rdy/out6 qfp - 100 21 20 17 16 19 18 15 14 13 12 11 26 25 24 23 22 27 28 29 4 356 29 710 80 51 58 71 70 67 66 69 68 65 64 63 62 61 76 75 74 73 72 77 78 79 54 53 55 56 52 59 57 60 p57/an15/da01 p74/an20/int4 p73/an19/int3 p72/an18/int2 p60/an0/ppg0(1) p61/an1/ppg2(3) p62/an2/ppg4(5) p63/an3/ppg6(7) p64/an4/ppg8(9) p65/an5/ppga(b) p66/an6/ppgc(d) p67/an7/ppge(f) vss p70/an16/int0 p71/an17/int1 avcc avrh avrl avss
document number: 002-04498 rev. *a page 11 of 92 mb90340e series (continued) this pin assignment is for using mb90v34 0e-101/102 via probecable as mb90340e. (top view) (fpt-100p-m20) * : x0a, x1a : mb90v340e-102 p40, p41 : mb90v340e-101 75 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15/sck4 p16/ad14/sot4 p15/ad13/sin4 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p75/an21/int5 p74/an20/int4 p73/an19/int3 p72/an18/int2 p71/an17/int1 p70/an16/int0 vss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p63/an3/ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2(3) p60/an0/ppg0(1) avss avrl avrh avcc p57/an15/da01 p00/ad00/int8 pa1/tx0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/an23/int7 p76/an22/int6 md0 p26/a22/in2 p27/a23/in3 p30/ale/in4 p34/hrq/out4 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47/scl1 p46/sda1 p45/scl0/frck1 p44/s da0/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a * p40/x0a * p37/clk/out7 p36/rdy/out6 lqfp - 100 99 p24/a20/in0 100 p25/a21/in1 28 p56/an14/da00 27 p55/an13 26 p54/an12/tot3 49 md2 50 md1 78 p03/ad03/int11 77 p02/ad02/int10 76 p01/ad01/int9 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 58 59 55 56 57 54 53 52 51 1 2 3 4 5 6 7 8 9 10111213141516 18 17 21 20 19 22 23 24 25 rst p31/rd/in5 p32/wrl/wr/rx2/int10r p33/wrh/tx2 p35/hak/out5
document number: 002-04498 rev. *a page 12 of 92 mb90340e series 3. pin description (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 1 to 4 99 to 2 p24 to p27 g general purpose i/o pins. the register c an be set to select whether to use a pull-up resistor.in external bus mode, the pin is enabled as a general-purpose i/o port when the corresponding bit in the ex ternal address output control register (hacr) is 1. a20 to a23 output pins of the external address bus. when the corresponding bit in the external address output control register (hacr) is 0, the pins are enabled as high address output pins (a20 to a23). in0 to in3 trigger input pins for input captures. 53 p30 g general purpose i/o pin.the register ca n be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ale address latch enable output pin. this f unction is enabled when the external bus is enabled. in4 trigger input pin for input capture. 64 p31 g general purpose i/o pin.the register ca n be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. rd external read strobe output pin. this func tion is enabled when the external bus is enabled. in5 trigger input pin for input capture. 75 p32 g general purpose i/o pin. the register ca n be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or when the wr /wrl pin output is disabled. wr / wrl write strobe output pin for the external data bus. this function is enabled when both the external bus and the wr /wrl pin output are enabled. wrl is used to write-strobe 8 lower bits of the data bus in 16-bit access while wr is used to write-strobe 8 bits of the data bus in 8-bit access. int10r external interrupt request input pin. 86 p33 g general purpose i/o pin. the register ca n be set to select whether to use a pull-up resistor.this function is enabled either in single-chip mode or when the wrh pin output is disabled. wrh write strobe output pin for the upper 8 bits of the external data bus. this function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the wrh output pin is enabled.
document number: 002-04498 rev. *a page 13 of 92 mb90340e series (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 97 p34 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or when the hold function is disabled. hrq hold request input pin. this function is enabled when both the external bus and the hold function are enabled. out4 waveform output pin for output compare. 10 8 p35 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or when the hold function is disabled. hak hold acknowledge output pin. this func tion is enabled when both the external bus and the hold function are enabled. out5 waveform output pin for output compare. 11 9 p36 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or when the external ready function is disabled. rdy external ready input pin. this function is enabled when both the external bus and the external ready function are enabled. out6 waveform output pin for output compare. 12 10 p37 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or when the clock output is disabled. clk clock output pin. this function is enabled when both the external bus and clock output are enabled. out7 waveform output pin for output compare 13, 14 11, 12 p40, p41 f general purpose i/o pins. (devices with an s suffix in th e part number and or mb90v340e-101) x0a, x1a b oscillation pins for sub clock (devices without an s suffix in t he part number and or mb90v340e-102) 15 13 v cc ? power (3.5 v to 5.5 v) input pin 16 14 v ss ? gnd pin 17 15 c k this is the power supply stabilization ca pacitor this pin should be connected to a ceramic capacitor with a capacitance greater than or equal to 0.1 ? f. 18 16 p42 f general purpose i/o pin. in6 trigger input pin for input capture. rx1 rx input pin for can1 interface (mb90341e/342e/f342e/f345e only) int9r external interrupt request input pin
document number: 002-04498 rev. *a page 14 of 92 mb90340e series (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 19 17 p43 f general purpose i/o pin. in7 trigger input pin for input capture. tx1 tx output pin for can1 (mb90341e/342e/f342e/f345e only) 20 18 p44 h general purpose i/o pin. sda0 serial data i/o pin for i 2 c (devices with a c suffix in the part number) frck0 input pin for the 16-bit free-run timer 0 21 19 p45 h general purpose i/o pin. scl0 serial clock i/o pin for i 2 c (devices with a c suffix in the part number) frck1 input pin for the 16-bit free-run timer 22 20 p46 h general purpose i/o pin. sda1 serial data i/o pin for i 2 c (devices with a c suffix in the part number) 23 21 p47 h general purpose i/o pin. scl1 serial clock i/o pin for i 2 c (devices with a c suffix in the part number) 24 22 p50 o general purpose i/o pin. an8 analog input pin for the a/d converter sin2 serial data input pin for uart2 25 23 p51 i general purpose i/o pin. an9 analog input pin for the a/d converter sot2 serial data output pin for uart2 26 24 p52 i general purpose i/o pin. an10 analog input pin for the a/d converter sck2 clock i/o pin for uart2 27 25 p53 i general purpose i/o pin. an11 analog input pin for the a/d converter tin3 event input pin for the reload timer 28 26 p54 i general purpose i/o pin. an12 analog input pin for the a/d converter tot3 output pin for the reload timer 29 27 p55 i general purpose i/o pin. an13 analog input pin for the a/d converter 30, 31 28, 29 p56, p57 j general purpose i/o pins. an14, an15 analog input pins for the a/d converter 32 30 av cc k analog power input pin for the a/d converter
document number: 002-04498 rev. *a page 15 of 92 mb90340e series (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 33 31 avrh l reference voltage input pin for the a/d converter. this power supply must be turned on or off while a voltage higher than or equal to avrh is applied to av cc . 34 32 avrl k lower reference voltage input pin for the a/d converter 35 33 av ss k analog gnd pin for the a/d converter 36 to 43 34 to 41 p60 to p67 i general purpose i/o pins. an0 to an7 analog input pins for the a/d converter ppg0, 2, 4, 6, 8, a, c, e output pins for ppgs 44 42 v ss ? gnd pin 45 to 50 43 to 48 p70 to p75 i general purpose i/o pins. an16 to an21 analog input pins for the a/d converter (d evices with a c suffix in the part number) int0 to int5 external interrupt request input pins 51 49 md2 d input pin for specifying the operating mode. 52, 53 50, 51 md1, md0 c input pins for specifying the operating mode. 54 52 rst e reset input pin 55, 56 53, 54 p76, p77 i general purpose i/o pins. an22, an23 analog input pins for the a/d converter (d evices with a c suffix in the part number) int6, int7 external interrupt request input pins 57 55 p80 f general purpose i/o pin. tin0 event input pin for the reload timer adtg trigger input pin for the a/d converter int12r external interrupt request input pin 58 56 p81 f general purpose i/o pin. tot0 output pin for the reload timer ckot output pin for the clock monitor int13r external interrupt request input pin 59 57 p82 m general purpose i/o pin. sin0 serial data input pin for uart0 tin2 event input pin for the reload timer int14r external interrupt request input pin 60 58 p83 f general purpose i/o pin. sot0 serial data output pin for uart0 tot2 output pin for the reload timer
document number: 002-04498 rev. *a page 16 of 92 mb90340e series (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 61 59 p84 f general purpose i/o pin. sck0 clock i/o pin for uart0 int15r external interrupt request input pin 62 60 p85 m general purpose i/o pin. sin1 serial data input pin for uart1 63 61 p86 f general purpose i/o pin. sot1 serial data output pin for uart1 64 62 p87 f general purpose i/o pin. sck1 clock i/o pin for uart1 65 63 v cc ? power (3.5 v to 5.5 v) input pin 66 64 v ss ? gnd pin 67 to 70 65 to 68 p90 to p93 f general purpose i/o pins ppg1, 3, 5, 7 output pins for ppgs 71 to 74 69 to 72 p94 to p97 f general purpose i/o pins out0 to out3 waveform output pins for output co mpares. this function is enabled when the ocu enables waveform output. 75 73 pa0 f general purpose i/o pin. rx0 rx input pin for can0 interface int8r external interrupt request input pin 76 74 pa1 f general purpose i/o pin. tx0 tx output pin for can0 77 to 84 75 to 82 p00 to p07 g general purpose i/o pins. the register can be set to select whether to use a pull-up resistor. this functi on is enabled in single-chip mode. ad00 to ad07 i/o pins for 8 lower bits of the external address/data bus. this function is enabled when t he external bus is enabled. int8 to int15 external interrupt request input pins. 85 83 p10 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad08 i/o pin for the external address/data bus. this function is enabled when t he external bus is enabled. tin1 event input pin for the reload timer
document number: 002-04498 rev. *a page 17 of 92 mb90340e series (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 86 84 p11 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad09 i/o pin for the external addr ess/data bus. this function is enabled when the external bus is enabled. tot1 output pin for the reload timer 87 85 p12 n general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad10 i/o pin for the external addr ess/data bus. this function is enabled when the external bus is enabled. sin3 serial data input pin for uart3 int11r external interrupt request input pin 88 86 p13 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad11 i/o pin for the external addr ess/data bus. this function is enabled when the external bus is enabled. sot3 serial data output pin for uart3 89 87 p14 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad12 i/o pin for the external addr ess/data bus. this function is enabled when the external bus is enabled. sck3 clock i/o pin for uart3 90 88 v cc ? power (3.5 v to 5.5 v) input pin 91 89 v ss ? gnd pin 92 90 x1 a main clock output pin 93 91 x0 main clock input pin 94 92 p15 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad13 i/o pin for the external addr ess/data bus. this function is enabled when the external bus is enabled. 95 93 p16 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad14 i/o pin for the external addr ess/data bus. this function is enabled when the external bus is enabled.
document number: 002-04498 rev. *a page 18 of 92 mb90340e series (continued) 1 : fpt-100p-m06 2 : fpt-100p-m20 3 : for i/o circuit type, refer to ? i/o circuit type ?. pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 96 94 p17 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad15 i/o pin for the external address/data bus. this function is enabled when the external bus is enabled. 97 to 100 95 to 98 p20 to p23 g general purpose i/o pins. the register can be set to select whether to use a pull-up resistor.in external bus mode, the pin is enabled as a general-purpose i/o port when the corr esponding bit in the external address output control register (hacr) is 1. a16 to a19 output pins of the external addres s bus. when the corresponding bit in the external address output control register (hacr) is 0, the pins are enabled as high address output pins (a16 to a19). ppg9,ppgb,pp gd,ppgf output pins for ppgs
document number: 002-04498 rev. *a page 19 of 92 mb90340e series 4. i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed oscillation feedback resistor = approx. 1 m ? b oscillation circuit low-speed oscillation feedback resistor = approx. 10 m ? c ? mask rom and evaluation products: cmos hysteresis input pin ? flash memory products: cmos input pin d mask rom and evaluation products: ? cmos hysteresis input pin ? pull-down resistor value: approx. 50 k ? flash memory products: ? cmos input pin ? no pull-down e cmos hysteresis input pin pull-up resistor value: approx. 50 k ? standby control signal x1 x0 xout standby control signal x1a x0a xout cmos hysteresis inputs r pull-down resistor cmos hysteresis inputs r pull-up resistor cmos hysteresis inputs r
document number: 002-04498 rev. *a page 20 of 92 mb90340e series (continued) type circuit remarks f ? cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos hysteresis input (with function to disconnect input during standby) ? automotive input (with function to disconnect input during standby) g ? cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos hysteresis input (with function to disconnect input during standby) ? automotive input (with function to disconnect input during standby) ? ttl input (with function to disconnect input during standby) ? programmable pull-up resistor: 50 k ? approx. h ? cmos level output (i ol = 3 ma, i oh ? ? 3 ma) ? cmos hysteresis input (with function to disconnect input during standby) ? automotive input (with function to disconnect input during standby) cmos hysteresis input automotive input standby control for input shutdown pout nout r p-ch n-ch pull-up control cmos hysteresis input automotive input ttl input standby control for input shutdown pout nout r p-ch p-ch n-ch cmos hysteresis input automotive input standby control for input shutdown pout nout r n-ch p-ch
document number: 002-04498 rev. *a page 21 of 92 mb90340e series type circuit remarks i ? cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos hysteresis input (w ith function to disconnect input during standby) ? automotive input (with function to disconnect input during standby) ? a/d converter analog input j ? cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? d/a analog output ? cmos hysteresis input (w ith function to disconnect input during standby) ? automotive input (with function to disconnect input during standby) ? a/d converter analog input k power supply input protection circuit l ? a/d converter reference voltage power supply input pin, with the protection circuit ? flash memory devices do not have a protection circuit against v cc for pin avrh cmos hysteresis input automotive input standby control for input shutdown analog input pout nout r p-ch n-ch cmos hysteresis input automotive input standby control for input shutdown analog input analog output pout nout r p-ch n-ch n-ch p-ch ane avr ane n-ch p-ch
document number: 002-04498 rev. *a page 22 of 92 mb90340e series (continued) type circuit remarks m ? cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos input (with function to disconnect input during standby) ? automotive input (with function to disconnect input during standby) n ? cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos input (with function to disconnect input during standby) ? automotive input (with function to disconnect input during standby) ? ttl input (with function to disconnect input during standby) programmable pull-up resistor: 50 k ?? approx o ? cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos input (with function to disconnect input during standby) ? automotive input (with function to disconnect input during standby) ? a/d converter analog input cmos input automotive input standby control for input shutdown pout nout r p-ch n-ch pull-up control cmos input automotive input ttl input standby control for input shutdown pout nout r n-ch p-ch p-ch cmos input automotive input standby control for input shutdown analog input pout nout r n-ch p-ch
document number: 002-04498 rev. *a page 23 of 92 mb90340e series 5. handling devices 1.preventing latch-up cmos ic may suffer latch - up under the following conditions: ? a voltage higher than v cc or lower than v ss is applied to an input or output pin. ? a voltage higher than the rated voltage is applied between v cc and v ss pins. ? the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dras tically, causing thermal damage to the device. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage. 2.handling unused pins leaving unused input terminals open may lead to permanent damage due to malfunction and latch-up; pull up or pull down the terminals through the resistors of 2 k ? or more. 3.power supply pins (v cc /v ss ) ? if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected inside of the device to preven t malfunction such as latch-up. to reduce unnecessary radiation, prevent malfunctioning of the st robe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. connect v cc and v ss pins to the device from the current supply source at a possibly low impedance. ? as a measure against power supply noise, it is recommended to connect a capacitor of about 0.1 ? f as a bypass capacitor between v cc and v ss pins in the vicinity of v cc and v ss pins of the device. 4.mode pins (md0 to md2) connect the mode pins directly to v cc or v ss pins. to prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to v cc or v ss pins and to provide a low-impedance connection. vcc vss vss vcc vss vcc mb90340e series vcc vss vcc vss
document number: 002-04498 rev. *a page 24 of 92 mb90340e series 5. sequence for turning on the power supply to the a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an23) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d converter supply and analog inputs. in this ca se, make sure that the volta ge does not exceed avrh or av cc (turning on/off the analog and digital power supplies simultaneously is acceptable). 6.connection of unused a/d converter pins when the a/d converter is used connect unused pins of a/d converter to av cc ? v cc , av ss ? avrh ? avrl ? v ss . 7.crystal oscillator circuit the x0, x1 pins and x0a, x1a pins may be possible causes of abno rmal operation. make sure to provide bypass capacitors via the shortest distance from x0, x1 pins and x0a, x1a pins, crysta l oscillator (or ceramic oscillator) and ground lines, and make sur e, to the utmost effort, that the osci llation circuit lines do not cross the lines of other circuits. it is highly recommended to pro vide a printed circuit board art work surrounding x0, x1 pins and x0a, x1 a pins with a ground area for stabilizing the operation. for each of the mass-production products, request an oscillator evaluation from the manufacturer of the oscillator you are usin g. 8. pull-up/down resistors the mb90340e series does not support internal pull-up/down resistors (except for the pull-up resistors built into ports 0 to 3) . use external components where needed. 9.using external clock to use an external clock, drive the x0 pin and leave the x1 pin open. 10.precautions when not using a sub clock signal if you do not connect pins x0a and x1a to an oscillator, use pull-down handling on the x0a pin, and leave the x1a pin open. 11.notes on operation in pll clock mode if pll clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is n o external oscillator or the external clock input is stopped. perfo rmance of this operation, however, cannot be guaranteed. 12.notes on power-on to prevent the internal regulator circuit from malfunct ioning, set the voltage rise time during power-on to 50 ? s or more (0.2 v to 2.7 v) x0 x1 mb90340e series open
document number: 002-04498 rev. *a page 25 of 92 mb90340e series 13.stabilization of power supply voltage a sudden change in the supply voltage may cause the device to malfunction even within the v cc supply voltage operating range. therefore, the v cc supply voltage should be stabilized. for reference, the supply voltage should be controlled so that v cc ripple variations (peak- to-peak values) at commerci al frequencies (50 mhz/60 mhz) fall below 10 ? of the standard v cc supply voltage and the coefficient of fluctuation does not exce ed 0.1 v/ms at instant aneous power switching. 14.port 0 to port 3 output during power-on (external-bus mode) as shown below, when the power is turned on in external-bus mode , there is a possibility that outp ut signal of port 0 to port 3 might be unstable irrespective of the reset input. 15.notes on using the can function to use the can function, please set the direct bit of the can dir ect mode register (cdmr) to 1. 16.flash security function (except for mb90f346e) a security bit is located in the area of the flash memory. if protection code 01 h is written in the security bi t, the flash memory is in t he protected state by security. therefore please do not write 01 h in this address if you do not use the security function. refer to following table for the address of the security bit. 17.serial communication there is a possibility to receive wrong data due to th e noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. retransmit the data if an error occurs becaus e of applying the checksum to the last data in consideration of receiving wrong da ta due to the noise. flash memory size address of the security bit mb90f347e embedded 1 mbit flash memory fe0001 h mb90f342e mb90f349e embedded 2 mbits flash memory fc0001 h mb90f345e embedded 4 mbits flash memory f80001 h port0 to port3 outputs might be unstable port0 to port3 outputs = hi-z port0 to port3 v cc 1/2v cc
document number: 002-04498 rev. *a page 26 of 92 mb90340e series 6. block diagrams ? mb90v340e-101/102 ram lin-uart prescaler 8/10-bit 24 channels 16-bit reload free-run timer 0 clock controller input capture 8 channels output compare 8 channels can controller external interrupt 16lx cpu f 2 mc-16 bus x0,x1 rst sot4 to sot0 sck4 to sck0 sin4 to sin0 av cc av ss an23 to an0 avrh avrl adtg tin3 to tin0 tot3 to tot0 in7 to in0 out7 to out0 rx2 to rx0 tx2 to tx0 int15 to int8 external bus interface ad15 to ad00 a23 to a16 ale rd wr/wrl wrh hrq hak rdy clk x0a,x1a* 5 channels 10-bit d/a converter 2 channels da01, da00 frck0 frck1 8/16-bit ppg 16/8 channels ppgf to ppg0 i 2 c interface sda1, sda0 scl1, scl0 3 channels 5 channels 2 channels dmac * : only for mb90v340e-102 clock monitor ckot (int15r to int8r) int7 to int0 a/d converter 30 kbytes 16 channels 4 channels timer free-run timer 1
document number: 002-04498 rev. *a page 27 of 92 mb90340e series ? mb90341e(s), mb90341ce(s), mb90342e(s ), mb90342ce(s), mb90f342e(s), mb90f342ce(s), mb90f345e(s), mb90f345ce(s), mb90346e(s), mb9034 6ce(s), mb90f346e( s), mb90f346ce(s), mb903 47e(s), mb90347ce(s), mb90f347e(s), mb90f347ce(s), mb90348e (s), mb90348ce(s), mb90349e(s), mb90349c e(s), mb90f349e(s), mb90f349ce(s) ram rom/flash lin-uart prescaler 8/10-bit 16/24 16-bit reload free-run clock controller input capture 8 channels output compare 8 channels can controller external interrupt 16lx cpu f 2 mc-16 bus x0,x1 rst sot3 to sot0 sck3 to sck0 sin3 to sin0 av cc av ss an15 to an0 avrh avrl adtg tin3 to tin0 tot3 to tot0 in7 to in0 out7 to out0 rx0, rx1* 3 tx0, tx1* 3 int15 to int8 external bus interface ad15 to ad00 a23 to a16 ale rd wr /wrl wrh hrq hak rdy clk x0a,x1a* 1 64 k/128 k 4 channels free-run frck0 frck1 8/16-bit ppg 16/8 channels ppgf to ppg0 4 channels i 2 c interface sda1, sda0* 2 scl1, scl0* 2 2 channels an23 to an16* 2 2 k/6 k/16 k/ 20 kbytes 256 k/384 k/ *1 : only for devices with an s suffix in the part number *2 : only for devices with a c suffix in the part number *3 : only the mb90341e(s)/ 341ce(s)/ 342e(s)/ 342ce(s)/ f342e(s)/f342ce(s)/f345e(s)/ f345ce(s) are equipped with 2 can channels clock monitor ckot (int15r to int8r) int7 to int0 512 kbytes a/d converter 16 channels channels timer 4 channels 1/2 channels* 3 timer 0 timer 1 dmac
document number: 002-04498 rev. *a page 28 of 92 mb90340e series 7. memory map mb90v340e-101/102 mb90f345e(s)/f345ce(s) ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h fbffff h fb0000 h faffff h fa0000 h f9ffff h f90000 h f8ffff h f80000 h 00ffff h 008000 h 007fff h 007900 h 0078ff h 000100 h 0000ef h 000000 h ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h fbffff h fb0000 h faffff h fa0000 h f9ffff h f90000 h f8ffff h f80000 h 00ffff h 008000 h 007fff h 007900 h 0050ff h 000100 h 0000ef h 000000 h rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (f8 bank) rom (image of ff bank) peripheral ram 30 kbytes peripheral rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (f8 bank) rom (image of ff bank) peripheral ram 20 kbytes peripheral external access area external access area external access area external access area : not accessible
document number: 002-04498 rev. *a page 29 of 92 mb90340e series note: :an image of the data in the ff bank of rom is visible in the upper part of b ank 00, which makes it possible for the c compiler to use the small memory model. the lower 16 bits of addresses in the ff bank are the same as the lower 16 bits of addresses in the 00 bank so that tables stored in the ro m can be accessed without using the far specifier in the pointer declaration. for example, when the address 00c000 h is accessed, the data at ffc000 h in rom is actually accessed. the rom area in bank ff exceeds 32 kbytes, and its entire image cannot be shown in bank 00. as a result, the image between ff8000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff7fff h is visible only in bank ff. mb90342e(s)/342ce(s) mb90f342e(s)/f342ce(s) mb90349e(s)/349ce(s) mb90f349e(s)/f349ce(s) mb90341e(s)/341ce(s) mb90348e(s)/348ce(s) mb90347e(s)/347ce(s) mb90f347e(s)/f347ce(s) mb90346e(s)/346ce(s) mb90f346e(s)/f346ce(s) ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 003fff h 000100 h 008000 h ffffff h ff0000 h feffff h fe0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 003fff h 000100 h 008000 h ffffff h ff0000 h feffff h fe0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 0018ff h 000100 h 008000 h ffffff h ff0000 h feffff h fe0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 0008ff h 000100 h 008000 h rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) external access area rom (image of ff bank) peripheral ram 16 kbytes external access area peripheral : not accessible external access area rom (image of ff bank) peripheral ram 16 kbytes external access area peripheral external access area rom (image of ff bank) peripheral ram 6 kbytes external access area peripheral external access area rom (image of ff bank) peripheral ram 2 kbytes external access area peripheral rom (ff bank) rom (fe bank) rom (ff bank) rom (fe bank) rom (ff bank)
document number: 002-04498 rev. *a page 30 of 92 mb90340e series 8. i/o map (continued) address register abbreviation access resource name initial value 000000 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 000001 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 000002 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 000003 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 000004 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 000005 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 000006 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 000007 h port 7 data register pdr7 r/w port 7 xxxxxxxx b 000008 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 000009 h port 9 data register pdr9 r/w port 9 xxxxxxxx b 00000a h port a data register pdra r/w port a xxxxxxxx b 00000b h port 5 analog input enable register ader5 r/w port 5, a/d 11111111 b 00000c h port 6 analog input enable register ader6 r/w port 6, a/d 11111111 b 00000d h port 7 analog input enable register ader7 r/w port 7, a/d 11111111 b 00000e h input level select register 0 ilsr0 r/w ports xxxxxxxx b 00000f h input level select register 1 ilsr1 r/w ports xxxx0xxx b 000010 h port 0 direction register ddr0 r/w port 0 00000000 b 000011 h port 1 direction register ddr1 r/w port 1 00000000 b 000012 h port 2 direction register ddr2 r/w port 2 00000000 b 000013 h port 3 direction register ddr3 r/w port 3 00000000 b 000014 h port 4 direction register ddr4 r/w port 4 00000000 b 000015 h port 5 direction register ddr5 r/w port 5 00000000 b 000016 h port 6 direction register ddr6 r/w port 6 00000000 b 000017 h port 7 direction register ddr7 r/w port 7 00000000 b 000018 h port 8 direction register ddr8 r/w port 8 00000000 b 000019 h port 9 direction register ddr9 r/w port 9 00000000 b 00001a h port a direction register ddra r/w port a 00000100 b 00001b h reserved 00001c h port 0 pull-up control register pucr0 r/w port 0 00000000 b 00001d h port 1 pull-up control register pucr1 r/w port 1 00000000 b 00001e h port 2 pull-up control register pucr2 r/w port 2 00000000 b 00001f h port 3 pull-up control register pucr3 w, r/w port 3 00000000 b
document number: 002-04498 rev. *a page 31 of 92 mb90340e series (continued) address register abbreviation access resource name initial value 000020 h serial mode register 0 smr0 w,r/w uart0 00000000 b 000021 h serial control register 0 scr0 w,r/w 00000000 b 000022 h reception/transmission data register 0 rdr0/tdr0 r/w 00000000 b 000023 h serial status register 0 ssr0 r,r/w 00001000 b 000024 h extended communication control register 0 eccr0 r,w, r/w 000000xx b 000025 h extended status/control register 0 escr0 r/w 00000100 b 000026 h baud rate generator register 00 bgr00 r/w 00000000 b 000027 h baud rate generator register 01 bgr01 r/w 00000000 b 000028 h serial mode register 1 smr1 w,r/w uart1 00000000 b 000029 h serial control register 1 scr1 w,r/w 00000000 b 00002a h reception/transmission data register 1 rdr1/tdr1 r/w 00000000 b 00002b h serial status register 1 ssr1 r,r/w 00001000 b 00002c h extended communication control register 1 eccr1 r,w, r/w 000000xx b 00002d h extended status/control register 1 escr1 r/w 00000100 b 00002e h baud rate generator register 10 bgr10 r/w 00000000 b 00002f h baud rate generator register 11 bgr11 r/w 00000000 b 000030 h ppg 0 operation mode control register ppgc0 w,r/w 16-bit ppg 0/1 0x000xx1 b 000031 h ppg 1 operation mode control register ppgc1 w,r/w 0x000001 b 000032 h ppg 0/ppg 1 count clock select register ppg01 r/w 000000x0 b 000033 h reserved 000034 h ppg 2 operation mode control register ppgc2 w,r/w 16-bit ppg 2/3 0x000xx1 b 000035 h ppg 3 operation mode control register ppgc3 w,r/w 0x000001 b 000036 h ppg 2/ppg 3 count clock select register ppg23 r/w 000000x0 b 000037 h reserved 000038 h ppg 4 operation mode control register ppgc4 w,r/w 16-bit ppg 4/5 0x000xx1 b 000039 h ppg 5 operation mode control register ppgc5 w,r/w 0x000001 b 00003a h ppg 4/ppg 5 clock select register ppg45 r/w 000000x0 b 00003b h address detect control register 1 pacsr1 r/w address match detection 1 00000000 b 00003c h ppg 6 operation mode control register ppgc6 w,r/w 16-bit ppg 6/7 0x000xx1 b 00003d h ppg 7 operation mode control register ppgc7 w,r/w 0x000001 b 00003e h ppg 6/ppg 7 count clock control register ppg67 r/w 000000x0 b 00003f h reserved
document number: 002-04498 rev. *a page 32 of 92 mb90340e series (continued) address register abbreviation access resource name initial value 000040 h ppg 8 operation mode control register ppgc8 w,r/w 16-bit ppg 8/9 0x000xx1 b 000041 h ppg 9 operation mode control register ppgc9 w,r/w 0x000001 b 000042 h ppg 8/ppg 9 count clock control register ppg89 r/w 000000x0 b 000043 h reserved 000044 h ppg a operation mode control register ppgca w,r/w 16-bit ppg a/b 0x000xx1 b 000045 h ppg b operation mode control register ppgcb w,r/w 0x000001 b 000046 h ppg a/ppg b count clock select register ppgab r/w 000000x0 b 000047 h reserved 000048 h ppg c operation mode control register ppgcc w,r/w 16-bit ppg c/d 0x000xx1 b 000049 h ppg d operation mode control register ppgcd w,r/w 0x000001 b 00004a h ppg c/ppg d count clock select register ppgcd r/w 000000x0 b 00004b h reserved 00004c h ppg e operation mode control register ppgce w,r/w 16-bit ppg e/f 0x000xx1 b 00004d h ppg f operation mode control register ppgcf w,r/w 0x000001 b 00004e h ppg e/ppg f count clock select register ppgef r/w 000000x0 b 00004f h reserved 000050 h input capture control status 0/1 ics01 r/w input capture 0/1 00000000 b 000051 h input capture edge 0/1 ice01 r/w, r xxx0x0xx b 000052 h input capture control status 2/3 ics23 r/w input capture 2/3 00000000 b 000053 h input capture edge 2/3 ice23 r xxxxxxxx b 000054 h input capture control status 4/5 ics45 r/w input capture 4/5 00000000 b 000055 h input capture edge 4/5 ice45 r xxxxxxxx b 000056 h input capture control status 6/7 ics67 r/w input capture 6/7 00000000 b 000057 h input capture edge 6/7 ice67 r/w, r xxx000xx b 000058 h output compare control status 0 ocs0 r/w output compare 0/1 0000xx00 b 000059 h output compare control status 1 ocs1 r/w 0xx00000 b 00005a h output compare control status 2 ocs2 r/w output compare 2/3 0000xx00 b 00005b h output compare control status 3 ocs3 r/w 0xx00000 b 00005c h output compare control status 4 ocs4 r/w output compare 4/5 0000xx00 b 00005d h output compare control status 5 ocs5 r/w 0xx00000 b 00005e h output compare control status 6 ocs6 r/w output compare 6/7 0000xx00 b 00005f h output compare control status 7 ocs7 r/w 0xx00000 b
document number: 002-04498 rev. *a page 33 of 92 mb90340e series (continued) address register abbreviation access resource name initial value 000060 h timer control status 0 tmcsr0 r/w 16-bit reload timer 0 00000000 b 000061 h timer control status 0 tmcsr0 r/w xxxx0000 b 000062 h timer control status 1 tmcsr1 r/w 16-bit reload timer 1 00000000 b 000063 h timer control status 1 tmcsr1 r/w xxxx0000 b 000064 h timer control status 2 tmcsr2 r/w 16-bit reload timer 2 00000000 b 000065 h timer control status 2 tmcsr2 r/w xxxx0000 b 000066 h timer control status 3 tmcsr3 r/w 16-bit reload timer 3 00000000 b 000067 h timer control status 3 tmcsr3 r/w xxxx0000 b 000068 h a/d control status 0 adcs0 r/w a/d converter 000xxxx0 b 000069 h a/d control status 1 adcs1 r/w 0000000x b 00006a h a/d data 0 adcr0 r 00000000 b 00006b h a/d data 1 adcr1 r xxxxxx00 b 00006c h adc setting 0 adsr0 r/w 00000000 b 00006d h adc setting 1 adsr1 r/w 00000000 b 00006e h reserved 00006f h rom mirror function select romm w rom mirror xxxxxxx1 b 000070 h to 00008f h reserved for can controller 0/1. refer to ? can controllers ? 000090 h to 00009a h reserved 00009b h dma descriptor channel specified register dcsr r/w dma 00000000 b 00009c h dma status l register dsrl r/w 00000000 b 00009d h dma status h register dsrh r/w 00000000 b 00009e h address detect control register 0 pacsr0 r/w address match detection 0 00000000 b 00009f h delayed interrupt trigger/release register dirr r/w delayed interrupt xxxxxxx0 b 0000a0 h low-power mode control register lpmcr w,r/w low power control circuit 00011000 b 0000a1 h clock selection register ckscr r,r/w low power control circuit 11111100 b 0000a2 h , 0000a3 h reserved 0000a4 h dma stop status register dssr r/w dma 00000000 b
document number: 002-04498 rev. *a page 34 of 92 mb90340e series (continued) address register abbreviation access resource name initial value 0000a5 h automatic ready function select register arsr w external memory access 0011xx00 b 0000a6 h external address output control register hacr w 00000000 b 0000a7 h bus control signal selection register ecsr w 0000000x b 0000a8 h watchdog control register wdtc r,w watchdog timer xxxxx111 b 0000a9 h time base timer control register tbtc w,r/w time base timer 1xx00100 b 0000aa h watch timer control register wtc r,r/w watch timer 1x001000 b 0000ab h reserved 0000ac h dma enable l register derl r/w dma 00000000 b 0000ad h dma enable h register derh r/w 00000000 b 0000ae h flash control status register (flash memory devices only. otherwise reserved) fmcs r,r/w flash memory 000x0000 b 0000af h reserved 0000b0 h interrupt control register 00 icr00 w,r/w interrupt control 00000111 b 0000b1 h interrupt control register 01 icr01 w,r/w 00000111 b 0000b2 h interrupt control register 02 icr02 w,r/w 00000111 b 0000b3 h interrupt control register 03 icr03 w,r/w 00000111 b 0000b4 h interrupt control register 04 icr04 w,r/w 00000111 b 0000b5 h interrupt control register 05 icr05 w,r/w 00000111 b 0000b6 h interrupt control register 06 icr06 w,r/w 00000111 b 0000b7 h interrupt control register 07 icr07 w,r/w 00000111 b 0000b8 h interrupt control register 08 icr08 w,r/w 00000111 b 0000b9 h interrupt control register 09 icr09 w,r/w 00000111 b 0000ba h interrupt control register 10 icr10 w,r/w 00000111 b 0000bb h interrupt control register 11 icr11 w,r/w 00000111 b 0000bc h interrupt control register 12 icr12 w,r/w 00000111 b 0000bd h interrupt control register 13 icr13 w,r/w 00000111 b 0000be h interrupt control register 14 icr14 w,r/w 00000111 b 0000bf h interrupt control register 15 icr15 w,r/w 00000111 b 0000c0 h d/a converter data 0 dat0 r/w d/a converter xxxxxxxx b 0000c1 h d/a converter data 1 dat1 r/w xxxxxxxx b 0000c2 h d/a control 0 dacr0 r/w xxxxxxx0 b 0000c3 h d/a control 1 dacr1 r/w xxxxxxx0 b
document number: 002-04498 rev. *a page 35 of 92 mb90340e series (continued) address register abbreviation access resource name initial value 0000c4 h , 0000c5 h reserved 0000c6 h external interrupt enable 0 enir0 r/w external interrupt 0 00000000 b 0000c7 h external interrupt source 0 eirr0 r/w xxxxxxxx b 0000c8 h external interrupt level setting 0 elvr0 r/w 00000000 b 0000c9 h external interrupt level setting 0 elvr0 r/w 00000000 b 0000ca h external interrupt enable 1 enir1 r/w external interrupt 1 00000000 b 0000cb h external interrupt source 1 eirr1 r/w xxxxxxxx b 0000cc h external interrupt level setting 1 elvr1 r/w 00000000 b 0000cd h external interrupt level setting 1 elvr1 r/w 00000000 b 0000ce h external interrupt source select eissr r/w 00000000 b 0000cf h pll/sub clock control register psccr w pll xxxx0000 b 0000d0 h dma buffer address pointer l register bapl r/w dma xxxxxxxx b 0000d1 h dma buffer address pointer m register bapm r/w xxxxxxxx b 0000d2 h dma buffer address pointer h register baph r/w xxxxxxxx b 0000d3 h dma control register dmacs r/w xxxxxxxx b 0000d4 h i/o register address pointer l register ioal r/w xxxxxxxx b 0000d5 h i/o register address pointer h register ioah r/w xxxxxxxx b 0000d6 h data counter l register dctl r/w xxxxxxxx b 0000d7 h data counter h register dcth r/w xxxxxxxx b 0000d8 h serial mode register 2 smr2 w,r/w uart2 00000000 b 0000d9 h serial control register 2 scr2 w,r/w 00000000 b 0000da h reception/transmission data register 2 rdr2/tdr2 r/w 00000000 b 0000db h serial status register 2 ssr2 r,r/w 00001000 b 0000dc h extended communication control register 2 eccr2 r,w, r/w 000000xx b 0000dd h extended status control register 2 escr2 r/w 00000100 b 0000de h baud rate generator register 20 bgr20 r/w 00000000 b 0000df h baud rate generator register 21 bgr21 r/w 00000000 b 0000e0 h to 0000ef h reserved for can controller 2. refer to ? can controllers ? 0000f0 h to 0000ff h external
document number: 002-04498 rev. *a page 36 of 92 mb90340e series (continued) address register abbreviation access resource name initial value 007900 h reload register l0 prll0 r/w 16-bit ppg 0/1 xxxxxxxx b 007901 h reload register h0 prlh0 r/w xxxxxxxx b 007902 h reload register l1 prll1 r/w xxxxxxxx b 007903 h reload register h1 prlh1 r/w xxxxxxxx b 007904 h reload register l2 prll2 r/w 16-bit ppg 2/3 xxxxxxxx b 007905 h reload register h2 prlh2 r/w xxxxxxxx b 007906 h reload register l3 prll3 r/w xxxxxxxx b 007907 h reload register h3 prlh3 r/w xxxxxxxx b 007908 h reload register l4 prll4 r/w 16-bit ppg 4/5 xxxxxxxx b 007909 h reload register h4 prlh4 r/w xxxxxxxx b 00790a h reload register l5 prll5 r/w xxxxxxxx b 00790b h reload register h5 prlh5 r/w xxxxxxxx b 00790c h reload register l6 prll6 r/w 16-bit ppg 6/7 xxxxxxxx b 00790d h reload register h6 prlh6 r/w xxxxxxxx b 00790e h reload register l7 prll7 r/w xxxxxxxx b 00790f h reload register h7 prlh7 r/w xxxxxxxx b 007910 h reload register l8 prll8 r/w 16-bit ppg 8/9 xxxxxxxx b 007911 h reload register h8 prlh8 r/w xxxxxxxx b 007912 h reload register l9 prll9 r/w xxxxxxxx b 007913 h reload register h9 prlh9 r/w xxxxxxxx b 007914 h reload register la prlla r/w 16-bit ppg a/b xxxxxxxx b 007915 h reload register ha prlha r/w xxxxxxxx b 007916 h reload register lb prllb r/w xxxxxxxx b 007917 h reload register hb prlhb r/w xxxxxxxx b 007918 h reload register lc prllc r/w 16-bit ppg c/d xxxxxxxx b 007919 h reload register hc prlhc r/w xxxxxxxx b 00791a h reload register ld prlld r/w xxxxxxxx b 00791b h reload register hd prlhd r/w xxxxxxxx b 00791c h reload register le prlle r/w 16-bit ppg e/f xxxxxxxx b 00791d h reload register he prlhe r/w xxxxxxxx b 00791e h reload register lf prllf r/w xxxxxxxx b 00791f h reload register hf prlhf r/w xxxxxxxx b 007920 h input capture 0 ipcp0 r input capture 0/1 xxxxxxxx b 007921 h input capture 0 ipcp0 r xxxxxxxx b 007922 h input capture 1 ipcp1 r xxxxxxxx b 007923 h input capture 1 ipcp1 r xxxxxxxx b
document number: 002-04498 rev. *a page 37 of 92 mb90340e series (continued) address register abbreviation access resource name initial value 007924 h input capture 2 ipcp2 r input capture 2/3 xxxxxxxx b 007925 h input capture 2 ipcp2 r xxxxxxxx b 007926 h input capture 3 ipcp3 r xxxxxxxx b 007927 h input capture 3 ipcp3 r xxxxxxxx b 007928 h input capture 4 ipcp4 r input capture 4/5 xxxxxxxx b 007929 h input capture 4 ipcp4 r xxxxxxxx b 00792a h input capture 5 ipcp5 r xxxxxxxx b 00792b h input capture 5 ipcp5 r xxxxxxxx b 00792c h input capture 6 ipcp6 r input capture 6/7 xxxxxxxx b 00792d h input capture 6 ipcp6 r xxxxxxxx b 00792e h input capture 7 ipcp7 r xxxxxxxx b 00792f h input capture 7 ipcp7 r xxxxxxxx b 007930 h output compare 0 occp0 r/w output compare 0/1 xxxxxxxx b 007931 h output compare 0 occp0 r/w xxxxxxxx b 007932 h output compare 1 occp1 r/w xxxxxxxx b 007933 h output compare 1 occp1 r/w xxxxxxxx b 007934 h output compare 2 occp2 r/w output compare 2/3 xxxxxxxx b 007935 h output compare 2 occp2 r/w xxxxxxxx b 007936 h output compare 3 occp3 r/w xxxxxxxx b 007937 h output compare 3 occp3 r/w xxxxxxxx b 007938 h output compare 4 occp4 r/w output compare 4/5 xxxxxxxx b 007939 h output compare 4 occp4 r/w xxxxxxxx b 00793a h output compare 5 occp5 r/w xxxxxxxx b 00793b h output compare 5 occp5 r/w xxxxxxxx b 00793c h output compare 6 occp6 r/w output compare 6/7 xxxxxxxx b 00793d h output compare 6 occp6 r/w xxxxxxxx b 00793e h output compare 7 occp7 r/w xxxxxxxx b 00793f h output compare 7 occp7 r/w xxxxxxxx b 007940 h timer data 0 tcdt0 r/w free-run timer 0 00000000 b 007941 h timer data 0 tcdt0 r/w 00000000 b 007942 h timer control status 0 tccsl0 r/w 00000000 b 007943 h timer control status 0 tccsh0 r/w 0xxxxxxx b 007944 h timer data 1 tcdt1 r/w free-run timer 1 00000000 b 007945 h timer data 1 tcdt1 r/w 00000000 b 007946 h timer control status 1 tccsl1 r/w 00000000 b 007947 h timer control status 1 tccsh1 r/w 0xxxxxxx b
document number: 002-04498 rev. *a page 38 of 92 mb90340e series (continued) address register abbreviation access resource name initial value 007948 h timer 0/reload 0 tmr0/tmrlr0 r/w 16-bit reload timer 0 xxxxxxxx b 007949 h r/w xxxxxxxx b 00794a h timer 1/reload 1 tmr1/tmrlr1 r/w 16-bit reload timer 1 xxxxxxxx b 00794b h r/w xxxxxxxx b 00794c h timer 2/reload 2 tmr2/tmrlr2 r/w 16-bit reload timer 2 xxxxxxxx b 00794d h r/w xxxxxxxx b 00794e h timer 3/reload 3 tmr3/tmrlr3 r/w 16-bit reload timer 3 xxxxxxxx b 00794f h r/w xxxxxxxx b 007950 h serial mode register 3 smr3 w,r/w uart3 00000000 b 007951 h serial control register 3 scr3 w,r/w 00000000 b 007952 h reception/transmission data register 3 rdr3/tdr3 r/w 00000000 b 007953 h serial status register 3 ssr3 r,r/w 00001000 b 007954 h extended communication control register 3 eccr3 r,w, r/w 000000xx b 007955 h extended status control register escr3 r/w 00000100 b 007956 h baud rate generator register 30 bgr30 r/w 00000000 b 007957 h baud rate generator register 31 bgr31 r/w 00000000 b 007958 h serial mode register 4 smr4 w,r/w uart4 00000000 b 007959 h serial control register 4 scr4 w,r/w 00000000 b 00795a h reception/transmission data register 4 rdr4/tdr4 r/w 00000000 b 00795b h serial status register 4 ssr4 r,r/w 00001000 b 00795c h extended communication control register 4 eccr4 r,w, r/w 000000xx b 00795d h extended status control register escr4 r/w 00000100 b 00795e h baud rate generator register 40 bgr40 r/w 00000000 b 00795f h baud rate generator register 41 bgr41 r/w 00000000 b 007960 h to 00796b h reserved 00796c h clock output enable register clkr r/w clock monitor xxxx0000 b 00796d h reserved 00796e h can direct mode register cdmr r/w can clock sync xxxxxxx0 b 00796f h can switch register canswr r/w can 0/1 xxxxxx00 b
document number: 002-04498 rev. *a page 39 of 92 mb90340e series (continued) address register abbreviation access resource name initial value 007970 h i 2 c bus status register 0 ibsr0 r i 2 c interface 0 00000000 b 007971 h i 2 c bus control register 0 ibcr0 w,r/w 00000000 b 007972 h i 2 c 10-bit slave address register 0 itbal0 r/w 00000000 b 007973 h itbah0 r/w 00000000 b 007974 h i 2 c 10-bit slave address mask register 0 itmkl0 r/w 11111111 b 007975 h itmkh0 r/w 00111111 b 007976 h i 2 c 7-bit slave address register 0 isba0 r/w 00000000 b 007977 h i 2 c 7-bit slave address mask register 0 ismk0 r/w 01111111 b 007978 h i 2 c data register 0 idar0 r/w 00000000 b 007979 h , 00797a h reserved 00797b h i 2 c clock control register 0 iccr0 r/w i 2 c interface 0 00011111 b 00797c h to 00797f h reserved 007980 h i 2 c bus status register 1 ibsr1 r i 2 c interface 1 00000000 b 007981 h i 2 c bus control register 1 ibcr1 w,r/w 00000000 b 007982 h i 2 c 10-bit slave address register 1 itbal1 r/w 00000000 b 007983 h itbah1 r/w 00000000 b 007984 h i 2 c 10-bit slave address mask register 1 itmkl1 r/w 11111111 b 007985 h itmkh1 r/w 00111111 b 007986 h i 2 c 7-bit slave address register 1 isba1 r/w 00000000 b 007987 h i 2 c 7-bit slave address mask register 1 ismk1 r/w 01111111 b 007988 h i 2 c data register 1 idar1 r/w 00000000 b 007989 h , 00798a h reserved 00798b h i 2 c clock control register 1 iccr1 r/w i 2 c interface 1 00011111 b 00798c h to 0079c1 h reserved 0079c2 h clock modulator control register cmcr r, r/w clock modulator 0001x000 b 0079c3 h to 0079df h reserved
document number: 002-04498 rev. *a page 40 of 92 mb90340e series (continued) note: ? initial value of ?x? represents unknown value. ? any write access to reserved addr esses in i/o map should not be performed. a read access to reserved addresses results in reading ?x?. address register abbreviation access resource name initial value 0079e0 h detect address setting 0 padr0 r/w address match detection 0 xxxxxxxx b 0079e1 h detect address setting 0 padr0 r/w xxxxxxxx b 0079e2 h detect address setting 0 padr0 r/w xxxxxxxx b 0079e3 h detect address setting 1 padr1 r/w xxxxxxxx b 0079e4 h detect address setting 1 padr1 r/w xxxxxxxx b 0079e5 h detect address setting 1 padr1 r/w xxxxxxxx b 0079e6 h detect address setting 2 padr2 r/w xxxxxxxx b 0079e7 h detect address setting 2 padr2 r/w xxxxxxxx b 0079e8 h detect address setting 2 padr2 r/w xxxxxxxx b 0079e9 h to 0079ef h reserved 0079f0 h detect address setting 3 padr3 r/w address match detection 1 xxxxxxxx b 0079f1 h detect address setting 3 padr3 r/w xxxxxxxx b 0079f2 h detect address setting 3 padr3 r/w xxxxxxxx b 0079f3 h detect address setting 4 padr4 r/w xxxxxxxx b 0079f4 h detect address setting 4 padr4 r/w xxxxxxxx b 0079f5 h detect address setting 4 padr4 r/w xxxxxxxx b 0079f6 h detect address setting 5 padr5 r/w xxxxxxxx b 0079f7 h detect address setting 5 padr5 r/w xxxxxxxx b 0079f8 h detect address setting 5 padr5 r/w xxxxxxxx b 0079f9 h to 0079ff h reserved 007a00 h to 007aff h reserved for can controller 0. refer to ? can controllers 007b00 h to 007bff h reserved for can controller 0. refer to ? can controllers ? 007c00 h to 007cff h reserved for can controller 1. refer to ? can controllers ? 007d00 h to 007dff h reserved for can controller 1. refer to ? can controllers ? 007e00 h to 007fff h reserved
document number: 002-04498 rev. *a page 41 of 92 mb90340e series 9. can controllers the can controller has the following features: ? conforms to can specification version 2.0 part a and b ? supports transmission/reception in standard frame and extended frame formats ? supports transmission of data fr ames by receiving remote frames ? 16 transmission/reception message buffers ? 29-bit id and 8-byte data ? multi-level message buffer configuration ? provides full-bit comparison, full-bit ma sk, acceptance register 0/acceptance regi ster 1 for each message buffer as id acceptance mask ? two acceptance mask registers in either st andard frame format or extended frame formats ? bit rate programmable from 10 kbps to 2 mbps (when input clock is at 16 mhz) list of control registers (1) address register abbreviation access initial value can0 can1 000070 h 000080 h message buffer valid register bvalr r/w 00000000 b 00000000 b 000071 h 000081 h 000072 h 000082 h transmit request register treqr r/w 00000000 b 00000000 b 000073 h 000083 h 000074 h 000084 h transmit cancel register tcanr w 00000000 b 00000000 b 000075 h 000085 h 000076 h 000086 h transmission complete register tcr r/w 00000000 b 00000000 b 000077 h 000087 h 000078 h 000088 h receive complete register rcr r/w 00000000 b 00000000 b 000079 h 000089 h 00007a h 00008a h remote request receiving register rrtrr r/w 00000000 b 00000000 b 00007b h 00008b h 00007c h 00008c h receive overrun register rovrr r/w 00000000 b 00000000 b 00007d h 00008d h 00007e h 00008e h reception interrupt enable register rier r/w 00000000 b 00000000 b 00007f h 00008f h
document number: 002-04498 rev. *a page 42 of 92 mb90340e series list of control registers (2) address register abbreviation access initial value can0 can1 007b00 h 007d00 h control status register csr r/w, w r/w, r 0xxxx0x1 b 00xxx000 b 007b01 h 007d01 h 007b02 h 007d02 h last event indicator register leir r/w 000x0000 b xxxxxxxx b 007b03 h 007d03 h 007b04 h 007d04 h receive and transmit error counter rtec r 00000000 b 00000000 b 007b05 h 007d05 h 007b06 h 007d06 h bit timing register btr r/w 11111111 b x1111111 b 007b07 h 007d07 h 007b08 h 007d08 h ide register ider r/w xxxxxxxx b xxxxxxxx b 007b09 h 007d09 h 007b0a h 007d0a h transmit rtr register trtrr r/w 00000000 b 00000000 b 007b0b h 007d0b h 007b0c h 007d0c h remote frame receive waiting register rfwtr r/w xxxxxxxx b xxxxxxxx b 007b0d h 007d0d h 007b0e h 007d0e h transmit interrupt enable register tier r/w 00000000 b 00000000 b 007b0f h 007d0f h 007b10 h 007d10 h acceptance mask select register amsr r/w xxxxxxxx b xxxxxxxx b 007b11 h 007d11 h 007b12 h 007d12 h xxxxxxxx b xxxxxxxx b 007b13 h 007d13 h 007b14 h 007d14 h acceptance mask register 0 amr0 r/w xxxxxxxx b xxxxxxxx b 007b15 h 007d15 h 007b16 h 007d16 h xxxxxxxx b xxxxxxxx b 007b17 h 007d17 h 007b18 h 007d18 h acceptance mask register 1 amr1 r/w xxxxxxxx b xxxxxxxx b 007b19 h 007d19 h 007b1a h 007d1a h xxxxxxxx b xxxxxxxx b 007b1b h 007d1b h
document number: 002-04498 rev. *a page 43 of 92 mb90340e series list of message buffers (id registers) (1) address register abbreviation access initial value can0 can1 007a00 h to 007a1f h 007c00 h to 007c1f h general- purpose ram ? r/w xxxxxxxx b to xxxxxxxx b 007a20 h 007c20 h id register 0 idr0 r/w xxxxxxxx b xxxxxxxx b 007a21 h 007c21 h 007a22 h 007c22 h xxxxxxxx b xxxxxxxx b 007a23 h 007c23 h 007a24 h 007c24 h id register 1 idr1 r/w xxxxxxxx b xxxxxxxx b 007a25 h 007c25 h 007a26 h 007c26 h xxxxxxxx b xxxxxxxx b 007a27 h 007c27 h 007a28 h 007c28 h id register 2 idr2 r/w xxxxxxxx b xxxxxxxx b 007a29 h 007c29 h 007a2a h 007c2a h xxxxxxxx b xxxxxxxx b 007a2b h 007c2b h 007a2c h 007c2c h id register 3 idr3 r/w xxxxxxxx b xxxxxxxx b 007a2d h 007c2d h 007a2e h 007c2e h xxxxxxxx b xxxxxxxx b 007a2f h 007c2f h 007a30 h 007c30 h id register 4 idr4 r/w xxxxxxxx b xxxxxxxx b 007a31 h 007c31 h 007a32 h 007c32 h xxxxxxxx b xxxxxxxx b 007a33 h 007c33 h 007a34 h 007c34 h id register 5 idr5 r/w xxxxxxxx b xxxxxxxx b 007a35 h 007c35 h 007a36 h 007c36 h xxxxxxxx b xxxxxxxx b 007a37 h 007c37 h 007a38 h 007c38 h id register 6 idr6 r/w xxxxxxxx b xxxxxxxx b 007a39 h 007c39 h 007a3a h 007c3a h xxxxxxxx b xxxxxxxx b 007a3b h 007c3b h 007a3c h 007c3c h id register 7 idr7 r/w xxxxxxxx b xxxxxxxx b 007a3d h 007c3d h 007a3e h 007c3e h xxxxxxxx b xxxxxxxx b 007a3f h 007c3f h
document number: 002-04498 rev. *a page 44 of 92 mb90340e series list of message buffers (id registers) (2) address register abbreviation access initial value can0 can1 007a40 h 007c40 h id register 8 idr8 r/w xxxxxxxx b xxxxxxxx b 007a41 h 007c41 h 007a42 h 007c42 h xxxxxxxx b xxxxxxxx b 007a43 h 007c43 h 007a44 h 007c44 h id register 9 idr9 r/w xxxxxxxx b xxxxxxxx b 007a45 h 007c45 h 007a46 h 007c46 h xxxxxxxx b xxxxxxxx b 007a47 h 007c47 h 007a48 h 007c48 h id register 10 idr10 r/w xxxxxxxx b xxxxxxxx b 007a49 h 007c49 h 007a4a h 007c4a h xxxxxxxx b xxxxxxxx b 007a4b h 007c4b h 007a4c h 007c4c h id register 11 idr11 r/w xxxxxxxx b xxxxxxxx b 007a4d h 007c4d h 007a4e h 007c4e h xxxxxxxx b xxxxxxxx b 007a4f h 007c4f h 007a50 h 007c50 h id register 12 idr12 r/w xxxxxxxx b xxxxxxxx b 007a51 h 007c51 h 007a52 h 007c52 h xxxxxxxx b xxxxxxxx b 007a53 h 007c53 h 007a54 h 007c54 h id register 13 idr13 r/w xxxxxxxx b xxxxxxxx b 007a55 h 007c55 h 007a56 h 007c56 h xxxxxxxx b xxxxxxxx b 007a57 h 007c57 h 007a58 h 007c58 h id register 14 idr14 r/w xxxxxxxx b xxxxxxxx b 007a59 h 007c59 h 007a5a h 007c5a h xxxxxxxx b xxxxxxxx b 007a5b h 007c5b h 007a5c h 007c5c h id register 15 idr15 r/w xxxxxxxx b xxxxxxxx b 007a5d h 007c5d h 007a5e h 007c5e h xxxxxxxx b xxxxxxxx b 007a5f h 007c5f h
document number: 002-04498 rev. *a page 45 of 92 mb90340e series list of message buffers (dlc registers and data registers) (1) address register abbreviation access initial value can0 can1 007a60 h 007c60 h dlc register 0 dlcr0 r/w xxxxxxxx b 007a61 h 007c61 h 007a62 h 007c62 h dlc register 1 dlcr1 r/w xxxxxxxx b 007a63 h 007c63 h 007a64 h 007c64 h dlc register 2 dlcr2 r/w xxxxxxxx b 007a65 h 007c65 h 007a66 h 007c66 h dlc register 3 dlcr3 r/w xxxxxxxx b 007a67 h 007c67 h 007a68 h 007c68 h dlc register 4 dlcr4 r/w xxxxxxxx b 007a69 h 007c69 h 007a6a h 007c6a h dlc register 5 dlcr5 r/w xxxxxxxx b 007a6b h 007c6b h 007a6c h 007c6c h dlc register 6 dlcr6 r/w xxxxxxxx b 007a6d h 007c6d h 007a6e h 007c6e h dlc register 7 dlcr7 r/w xxxxxxxx b 007a6f h 007c6f h 007a70 h 007c70 h dlc register 8 dlcr8 r/w xxxxxxxx b 007a71 h 007c71 h 007a72 h 007c72 h dlc register 9 dlcr9 r/w xxxxxxxx b 007a73 h 007c73 h 007a74 h 007c74 h dlc register 10 dlcr10 r/w xxxxxxxx b 007a75 h 007c75 h 007a76 h 007c76 h dlc register 11 dlcr11 r/w xxxxxxxx b 007a77 h 007c77 h 007a78 h 007c78 h dlc register 12 dlcr12 r/w xxxxxxxx b 007a79 h 007c79 h 007a7a h 007c7a h dlc register 13 dlcr13 r/w xxxxxxxx b 007a7b h 007c7b h 007a7c h 007c7c h dlc register 14 dlcr14 r/w xxxxxxxx b 007a7d h 007c7d h 007a7e h 007c7e h dlc register 15 dlcr15 r/w xxxxxxxx b 007a7f h 007c7f h
document number: 002-04498 rev. *a page 46 of 92 mb90340e series list of message buffers (dlc registers and data registers) (2) address register abbreviation access initial value can0 can1 007a80 h to 007a87 h 007c80 h to 007c87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b 007a88 h to 007a8f h 007c88 h to 007c8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 007a90 h to 007a97 h 007c90 h to 007c97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 007a98 h to 007a9f h 007c98 h to 007c9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 007aa0 h to 007aa7 h 007ca0 h to 007ca7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 007aa8 h to 007aaf h 007ca8 h to 007caf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 007ab0 h to 007ab7 h 007cb0 h to 007cb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b 007ab8 h to 007abf h 007cb8 h to 007cbf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 007ac0 h to 007ac7 h 007cc0 h to 007cc7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 007ac8 h to 007acf h 007cc8 h to 007ccf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b 007ad0 h to 007ad7 h 007cd0 h to 007cd7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 007ad8 h to 007adf h 007cd8 h to 007cdf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 007ae0 h to 007ae7 h 007ce0 h to 007ce7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 007ae8 h to 007aef h 007ce8 h to 007cef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b
document number: 002-04498 rev. *a page 47 of 92 mb90340e series list of message buffers (dlc registers and data registers) (3) address register abbreviation access initial value can0 can1 007af0 h to 007af7 h 007cf0 h to 007cf7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 007af8 h to 007aff h 007cf8 h to 007cff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b
document number: 002-04498 rev. *a page 48 of 92 mb90340e series 10. interrupt factors, interrupt vectors, in terrupt control register (continued) interrupt cause ei 2 os support dma channel number interrupt vector interrupt control register number address number address reset n ? #08 ffffdc h ?? int9 instruction n ? #09 ffffd8 h ?? exception n ? #10 ffffd4 h ?? can 0 rx n ? #11 ffffd0 h icr00 0000b0 h can 0 tx/ns n ? #12 ffffcc h can 1 rx / input capture 6 y1 ? #13 ffffc8 h icr01 0000b1 h can 1 tx/ns / input capture 7 y1 ? #14 ffffc4 h can 2 rx / i 2 c0 n ? #15 ffffc0 h icr02 0000b2 h can 2 tx/ns n ? #16 ffffbc h 16-bit reload timer 0 y1 0 #17 ffffb8 h icr03 0000b3 h 16-bit reload timer 1 y1 1 #18 ffffb4 h 16-bit reload timer 2 y1 2 #19 ffffb0 h icr04 0000b4 h 16-bit reload timer 3 y1 ? #20 ffffac h ppg 0/1/4/5 n ? #21 ffffa8 h icr05 0000b5 h ppg 2/3/6/7 n ? #22 ffffa4 h ppg 8/9/c/d n ? #23 ffffa0 h icr06 0000b6 h ppg a/b/e/f n ? #24 ffff9c h time base timer n ? #25 ffff98 h icr07 0000b7 h external interrupt 0 to 3, 8 to 11 y1 3 #26 ffff94 h watch timer n ? #27 ffff90 h icr08 0000b8 h external interrupt 4 to 7, 12 to 15 y1 4 #28 ffff8c h a/d converter y1 5 #29 ffff88 h icr09 0000b9 h free-run timer 0 / free-run timer 1 n ? #30 ffff84 h input capture 4/5 / i 2 c1 y1 6 #31 ffff80 h icr10 0000ba h output compare 0/1/4/5 y1 7 #32 ffff7c h input capture 0 to 3 y1 8 #33 ffff78 h icr11 0000bb h output compare 2/3/6/7 y1 9 #34 ffff74 h uart 0 rx y2 10 #35 ffff70 h icr12 0000bc h uart 0 tx y1 11 #36 ffff6c h uart 1 rx / uart 3 rx y2 12 #37 ffff68 h icr13 0000bd h uart 1 tx / uart 3 tx y1 13 #38 ffff64 h
document number: 002-04498 rev. *a page 49 of 92 mb90340e series (continued) y1 : usable y2 : usable, with ei 2 os stop function n : unusable note: ? the peripheral resources sharing the icr register have the same interrupt level. ? when two peripheral resources shar e the icr register, only one can us e extended intelligent i/o service at a time. ? when either of the two peripheral resources sharing the icr register specifies extend ed intelligent i/o service, the other one cannot use interrupts. interrupt cause ei 2 os support dma channel number interrupt vector interrupt control register number address number address uart 2 rx / uart 4 rx y2 14 #39 ffff60 h icr14 0000be h uart 2 tx / uart 4 tx y1 15 #40 ffff5c h flash memory n ? #41 ffff58 h icr15 0000bf h delayed interrupt n ? #42 ffff54 h
document number: 002-04498 rev. *a page 50 of 92 mb90340e series 11. electrical characteristics 11.1 absolute maximum ratings *1: this parameter is based on v ss ? av ss ? 0 v *2: set av cc and v cc to the same voltage. make sure that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *3: v i and v o should not exceed v cc ? 0.3 v. v i should not exceed the specified ratings. however if the maximu m current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4: applicable to pins: p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0, pa1 *5: ? applicable to pins: p00 to p07, p10 to p 17, p20 to p27, p30 to p37, p40 to p47, p50 to p57 (evaluation device : p50 to p55) , p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 to pa1 ? use within recommended operating conditions. ? use with dc voltage (current) ? the ? b signal should always be applied by using a limiting resistance placed between the ? b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the ? b signal is applied, the input current to the microcontroller pin does not e xceed the rated value, either inst antaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the ? b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss ? 6.0 v av cc v ss ? 0.3 v ss ? 6.0 v v cc ? av cc * 2 avrh, avrl v ss ? 0.3 v ss ? 6.0 v av cc ? avrh, av cc ? avrl, avrh ? avrl input voltage* 1 v i v ss ? 0.3 v ss ? 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss ? 6.0 v *3 maximum clamp current i clamp ? 4.0 ? 4.0 ma *5 total maximum clamp current ? |i clamp | ? 40 ma *5 ?l? level maximum output current i ol ? 15 ma *4, *6 ?l? level average output current i olav ? 4ma*4, *7 ?l? level maximum overall output current ? i ol ? 100 ma *4 ?l? level average overall output current ? i olav ? 50 ma *4, *8 ?h? level maximum output current i oh ?? 15 ma *4, *6 ?h? level average output current i ohav ?? 4ma*4, *7 ?h? level maximum overall output current ? i oh ?? 100 ma *4 ?h? level average overall output current ? i ohav ?? 50 ma *4, *8 power consumption p d ? 450 mw operating temperature t a ? 40 ? 105 c storage temperature t stg ? 55 ? 150 c
document number: 002-04498 rev. *a page 51 of 92 mb90340e series (continued) ? note that if a ? b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the ? b input is applied during power-on, the powe r supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the ? b input pin open. ? sample recommended circuits: *6: the maximum output current is defined as the peak va lue of the current of any one of the corresponding pins. *7: the average output current is defined as the value of the average current flowing over 100 ms at any one of the correspondi ng pins. *8: the average total output current is defi ned as the value of the average current flo wing over 100 ms at all of the correspon ding pins. warning: semiconductor devices can be permanently da maged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits ? b input (0 v to 16 v) limiting resistance protective diode
document number: 002-04498 rev. *a page 52 of 92 mb90340e series 11.2 recommended operating conditions (v ss ? av ss ? 0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within th eir recommended operating condition ranges. operation outside these ra nges may adversely affect reliability an d could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outsi de the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 4.0 5.0 5.5 v under normal operation 3.5 5.0 5.5 v under normal operation, when not using the a/d converter and not flash programming. 4.5 5.0 5.5 v when external bus is used. 3.0 ? 5.5 v maintains ram data in stop mode smoothing capacitor c s 0.1 ? 1.0 ? f use a ceramic capacitor or capacitor of better ac characteristics. capacitor at the v cc should be greater than this capacitor. operating temperature t a ? 40 ?? 105 c c c s c pin connection diagram
document number: 002-04498 rev. *a page 53 of 92 mb90340e series 11.3 dc characteristics (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? av ss ? 0 v) (continued) parameter symb ol pin condition value unit remarks min typ max input h voltage (at v cc ? 5 v ? 10 ? ) v ihs ?? 0.8 v cc ? v cc ? 0.3 v port inputs if cmos hysteresis input levels are selected (except p12, p44, p45, p46, p47, p50, p82, p85) v iha ?? 0.8 v cc ? v cc ? 0.3 v port inputs if automotive input levels are selected v iht ?? 2.0 ? v cc ? 0.3 v port inputs if ttl input levels are selected v ihs ?? 0.7 v cc ? v cc ? 0.3 v p12, p50, p82, p85 inputs if cmos input levels are selected v ihi ?? 0.7 v cc ? v cc ? 0.3 v p44, p45, p46, p47 inputs if cmos hysteresis input levels are selected v ihr ?? 0.8 v cc ? v cc ? 0.3 v rst input pin (cmos hysteresis) v ihm ?? v cc ? 0.3 ? v cc ? 0.3 v md input pin input l voltage (at v cc ? 5 v ? 10 ? ) v ils ?? v ss ? 0.3 ? 0.2 v cc v port inputs if cmos hysteresis input levels are selected (except p12, p44, p45, p46, p47, p50, p82, p85) v ila ?? v ss ? 0.3 ? 0.5 v cc v port inputs if automotive input levels are selected v ilt ?? v ss ? 0.3 ? 0.8 v port inputs if ttl input levels are selected v ils ?? v ss ? 0.3 ? 0.3 v cc v p12, p50, p82, p85 inputs if cmos input levels are selected v ili ?? v ss ? 0.3 ? 0.3 v cc v p44, p45, p46, p47 inputs if cmos hysteresis input levels are selected v ilr ?? v ss ? 0.3 ? 0.2 v cc v rst input pin (cmos hysteresis) v ilm ?? v ss ? 0.3 ? v ss ? 0.3 v md input pin output h voltage v oh normal outputs v cc ? 4.5 v, i oh ? ? 4.0 ma v cc ? 0.5 ?? v output h voltage v ohi i 2 c current outputs v cc ? 4.5 v, i oh ? ? 3.0 ma v cc ? 0.5 ?? v output l voltage v ol normal outputs v cc ? 4.5 v, i ol ? 4.0 ma ?? 0.4 v output l voltage v oli i 2 c current outputs v cc ? 4.5 v, i ol ? 3.0 ma ?? 0.4 v
document number: 002-04498 rev. *a page 54 of 92 mb90340e series (continued) (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? av ss ? 0 v) * : the power supply current is measured with an external clock. parameter symbo l pin condition value unit remarks min typ max input leak current i il ? v cc ? 5.5 v, v ss ? v i ? v cc ? 1 ?? 1 ? a pull-up resistance r up p00 to p07, p10 to p17, p20 to p27, p30 to p37, rst ? 25 50 100 k ? pull-down resistance r down md2 ? 25 50 100 k ? except flash memory devices power supply current* i cc v cc v cc ? 5.0 v, internal frequency : 24 mhz, at normal operation. ? 55 70 ma v cc ? 5.0 v, internal frequency : 24 mhz, at writing flash memory. ? 70 85 ma flash memory devices v cc ? 5.0 v, internal frequency : 24 mhz, at erasing flash memory. ? 75 90 ma flash memory devices i ccs v cc ? 5.0 v, internal frequency : 24 mhz, in sleep mode. ? 25 35 ma i cts v cc ? 5.0 v, internal frequency : 2 mhz, in main timer mode ? 0.3 0.8 ma i ctspll6 v cc ? 5.0 v, internal frequency : 24 mhz, in pll timer mode, external frequency ? 4 mhz ? 47ma i ccl v cc = 5.0 v internal frequency : 8 khz, in sub operation t a = ? 25 ? c ? 70 140 ? a i ccls v cc = 5.0 v internal frequency : 8 khz, in sub sleep t a = ? 25 ? c ? 20 50 ? a i cct v cc = 5.0 v internal frequency : 8 khz, in watch mode t a = ? 25 ? c ? 10 35 ? a i cch v cc ? 5.0 v, in stop mode, t a ? ? 25 ? c ? 725 ? a input capacitance c in other than c, av cc , av ss , avrh, avrl, v cc , v ss ?? 515pf
document number: 002-04498 rev. *a page 55 of 92 mb90340e series 11.4 ac characteristics 11.4.1 clock timing (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? av ss ? 0 v) * : when selecting the pll clock, the range of clock fre quency is limited. use this product within the range as mentioned in ?relation between the external clock frequency and machine clock frequency?. parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz when using an oscillation circuit 4 ? 16 mhz pll multiplied by 1 when using an oscillation circuit 4 ? 12 mhz pll multiplied by 2 when using an oscillation circuit 4 ? 8mhz pll multiplied by 3 when using an oscillation circuit 4 ? 6mhz pll multiplied by 4 when using an oscillation circuit ?? 4mhz pll multiplied by 6 when using an oscillation circuit 3 ? 24 mhz when using an external clock* f cl x0a, x1a ? 32.768 100 khz clock cycle time t cyl x0, x1 62.5 ? 333 ns when using an oscillation circuit x0, x1 41.67 ? 333 ns when using an external clock t cyll x0a, x1a 10 30.5 ? ? s input clock pulse width p wh , p wl x0 10 ?? ns duty ratio is about 30 ? to 70 ? . p whl , p wll x0a 5 15.2 ? ? s input clock rise and fall time t cr , t cf x0 ?? 5 ns when using external clock internal operating clock frequency (machine clock) f cp ? 1.5 ? 24 mhz when using main clock f cpl ?? 8.192 50 khz when using sub clock internal operating clock cycle time (machine clock) t cp ? 41.67 ? 666 ns when using main clock t cpl ? 20 122.1 ? ? s when using sub clock
document number: 002-04498 rev. *a page 56 of 92 mb90340e series x0 t cyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t cyll t cf t cr 0. 8 v cc 0.2 v cc p whl p wll clock timing
document number: 002-04498 rev. *a page 57 of 92 mb90340e series guaranteed pll operation range guaranteed operation range of mb90340e series * : when using a crystal oscillator or ceramic oscillato r, the maximum oscillation clock frequency is 16 mhz 24 5.5 3.5 1.5 4 power supply voltage v cc (v) guaranteed operation range guaranteed pll operation range 4.0 guaranteed a/d converter operation range machine clock f cp (mhz) 24 4.0 16 12 3 4 12 24 internal clock f cp (mhz) external clock f c (mhz) * x 4 x 3 x 2 x 1 x 1/2 (pll off) 8 8 guaranteed oscillat ion frequency range 1.5 16 x 6
document number: 002-04498 rev. *a page 58 of 92 mb90340e series 11.4.2 reset standby input (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? av ss ? 0.0 v) * : the oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90 ? . for crystal oscillators, this time is between several ms and se veral tens of ms, for cerami c oscillators the time is between several hundred ? s and several ms, and for an external clock, the time is 0 ms. parameter symbol pin value unit remarks min max reset input time t rstl rst 500 ? ns under normal operation oscillation time of oscillator* ? 100 ? s ?? s in stop mode, sub clock mode, sub sleep mode and watch mode 100 ?? s in time timer mode t rstl 0.2 v cc 0.2 v cc 100 s rst x0 90% of amplitude instruction execution oscillation stabilization waiting time oscillation time of oscillator internal operation clock internal reset 0.2 v cc rst t rstl 0.2 v cc ? under normal operation: ? in stop mode, sub clock mode, sub sleep mode, watch mode:
document number: 002-04498 rev. *a page 59 of 92 mb90340e series 11.4.3 power on reset (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? av ss ? 0.0 v) note: : if you change the power supply voltage too rapidly, a power on reset may occur. we recommend that you startup smoothly by restraining voltages when changing the power su pply voltage during operation, as shown in the figure below. perform while not using the pll clock. ho wever, if voltage drops are within 1 v/ s, you can operate while using the pll clock. 11.4.4 clock output timing (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, f cp ? 24 mhz) parameter symbol pin condition value unit remarks min max power on rise time t r v cc ? 0.05 30 ms power off time t off v cc 1 ? ms waiting time until power-on parameter symbol pin condition value unit remarks min max cycle time t cyc clk ? 62.5 ? ns f cp ? 16 mhz 41.67 ? ns f cp ? 24 mhz clk ? ? clk ? t chcl clk ? 20 ? ns f cp ? 16 mhz 13 ? ns f cp ? 24 mhz v cc t r t off 2.7 v 0.2 v 0.2 v 0.2 v v cc v ss 3 v holds ram data we recommend a rise of 50 mv/ms maximum.
document number: 002-04498 rev. *a page 60 of 92 mb90340e series clk 2.4 v t cyc 2.4 v 0. 8 v t chcl
document number: 002-04498 rev. *a page 61 of 92 mb90340e series 11.4.5 bus timing (read) (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, f cp ? 24 mhz) parameter symbol pin condition value unit min max ale pulse width t lhll ale ? t cp /2 ? 10 ? ns valid address ? ale ? time t avll ale, a23 to a16, ad15 to ad00 t cp /2 ? 20 ? ns ale ? ? address valid time t llax ale, ad15 to ad00 t cp /2 ? 15 ? ns valid address ? rd ? time t avrl a23 to a16, ad15 to ad00, rd t cp ? 15 ? ns valid address ? valid data input t avdv a23 to a16, ad15 to ad00 ? 5 t cp /2 ? 60 ns rd pulse width t rlrh rd 3 t cp /2 ? 20 ? ns rd ? ? valid data input t rldv rd , ad15 to ad00 ? 3 t cp /2 ? 50 ns rd ? ? data hold time t rhdx rd , ad15 to ad00 0 ? ns rd ? ? ale ? time t rhlh rd , ale t cp /2 ? 15 ? ns rd ? ? address valid time t rhax rd , a23 to a16 t cp /2 ? 10 ? ns valid address ? clk ? time t avch a23 to a16, ad15 to ad00, clk t cp /2 ? 16 ? ns rd ? ? clk ? time t rlch rd , clk t cp /2 ? 15 ? ns ale ? ? rd ? time t llrl ale, rd t cp /2 ? 15 ? ns a23 to a16 0.8 v 2.4 v 2.4 v 0.8 v t rhax ad15 to ad00 0.8 v 2.4 v 2.4 v 0.8 v address v il v ih v ih v il read data t rhdx t rldv t avdv clk t avch 2.4 v t rlch 2.4 v ale 2.4 v t lhll 2.4 v t rhlh 0.8 v t llax 2.4 v t avll rd t llrl t rlrh 0.8 v 2.4 v t avrl 0.8 v
document number: 002-04498 rev. *a page 62 of 92 mb90340e series 11.4.6 bus timing (write) (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, f cp ? 24 mhz) parameter symbol pin condition value unit min max valid address ? wr ? time t avwl a23 to a16, ad15 to ad00, wr ? t cp ? 15 ? ns wr pulse width t wlwh wr 3 t cp /2 ? 20 ? ns valid data output ? wr ? time t dvwh ad15 to ad00, wr 3 t cp /2 ? 20 ? ns wr ? ? data hold time t whdx ad15 to ad00, wr 15 ? ns wr ? ? address valid time t whax a23 to a16, wr t cp /2 ? 10 ? ns wr ? ? ale ? time t whlh wr , ale t cp /2 ? 15 ? ns wr ? ? clk ? time t wlch wr , clk t cp /2 ? 15 ? ns clk t wlch 2.4 v ale t whlh 2.4 v wr (wrl , wrh ) t wlwh 0.8 v 2.4 v t avwl a23 to a16 0.8 v 2.4 v 2.4 v 0.8 v t whax ad15 to ad00 2.4 v 0.8 v address 0.8 v 2.4 v write data t dvwh 0.8 v 2.4 v t whdx
document number: 002-04498 rev. *a page 63 of 92 mb90340e series 11.4.7 ready input timing (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, f cp ? 24 mhz) note: : if the rdy setup time is insufficient, use the auto-ready function. parameter symbol pin test condition rated value unit remarks min max rdy setup time t ryhs rdy ? 45 ? ns f cp ? 16 mhz 32 ? ns f cp ? 24 mhz rdy hold time t ryhh rdy 0 ? ns clk 2.4 v ale rd/wr rdy when wait is not used. v ih v ih t ryhh rdy when wait is used. t ryhs v il
document number: 002-04498 rev. *a page 64 of 92 mb90340e series 11.4.8 hold timing (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v, f cp ? 24 mhz) note: : there is more than 1 cycle from when hrq reads in until the hak is changed. parameter symbol pin condition value unit min max pin floating ? hak ? time t xhal hak ? 30 t cp ns hak ? time ? pin valid time t hahv hak t cp 2 t cp ns hak each pin hi-z t hahv t xhal 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v
document number: 002-04498 rev. *a page 65 of 92 mb90340e series 11.4.9 lin-uart0/1/2/3 ? bit setting: escr:sces = 0, eccr:scde = 0 (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? 0 v) note: ? ac characteristic in clk synchronized mode. ? c l is load capacity value of pins when testing. ? t cp is internal operating clock cycle time (mac hine clock) . refer to ? (1) clock timing?. parameter symbol pin condition value unit min max serial clock cycle time t scyc sck0 to sck3 internal shift clock mode output pins are c l ? 80 pf ? 1 ttl. 5 t cp ? ns sck ? ? sot delay time t slovi sck0 to sck3, sot0 to sot3 ? 50 ? 50 ns valid sin ? sck ? t ivshi sck0 to sck3, sin0 to sin3 t cp + 80 ? ns sck ? ? valid sin hold time t shixi sck0 to sck3, sin0 to sin3 0 ? ns serial clock ?l? pulse width t shsl sck0 to sck3 external shift clock mode output pins are c l ? 80 pf ? 1 ttl. 3 t cp - t r ? ns serial clock ?h? pulse width t slsh sck0 to sck3 t cp + 10 ? ns sck ? ? sot delay time t slove sck0 to sck3, sot0 to sot3 ? 2 t cp + 60 ns valid sin ? sck ? t ivshe sck0 to sck3, sin0 to sin3 30 ? ns sck ? ? valid sin hold time t shixe sck0, sck1, sin0 to sin3 t cp + 30 ? ns sck fall time t f sck0 to sck3 ? 10 ns sck rise time t r sck0 to sck3 ? 10 ns s ck0 to sck3 2.4 v 0.8 v s ot0 to sot3 0.8 v 2.4 v 0.8 v t slovi s in0 to sin3 v il v ih v il v ih t scyc t ivshi t shixi ? internal shift clock mode
document number: 002-04498 rev. *a page 66 of 92 mb90340e series ? bit setting: escr:sces = 1, eccr:scde = 0 (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? 0 v) note: ? c l is load capacity value of pins when testing. ? t cp is internal operating clock cycle ti me (machine clock) . refer to ? clock timing ?. parameter symbol pin condition value unit min max serial clock cycle time t scyc sck0 to sck3 internal shift clock mode output pins are c l ? 80 pf ? 1 ttl. 5 t cp ? ns sck ? ? sot delay time t shovi sck0 to sck3, sot0 to sot3 ? 50 ? 50 ns valid sin ? sck ? t ivsli sck0 to sck3, sin0 to sin3 t cp + 80 ? ns sck ? ? valid sin hold time t slixi sck0 to sck3, sin0 to sin3 0 ? ns serial clock ?h? pulse width t shsl sck0 to sck3 external shift clock mode output pins are c l ? 80 pf ? 1 ttl. 3 t cp - t r ? ns serial clock ?l? pulse width t slsh sck0 to sck3 t cp + 10 ? ns sck ? ? sot delay time t shove sck0 to sck3, sot0 to sot3 ? 2 t cp + 60 ns valid sin ? sck ? t ivsle sck0 to sck3, sin0 to sin3 30 ? ns sck ? ? valid sin hold time t slixe sck0 to sck3, sin0 to sin3 t cp + 30 ? ns sck fall time t f sck0 to sck3 ? 10 ns sck rise time t r sck0 to sck3 ? 10 ns ? external shift clock mode sck0 to sck3 v ih v il sot0 to sot3 0.8 v 2.4 v t slove sin0 to sin3 v il v ih v il v ih v ih v il t r t f t shsl t slsh t ivshe t shixe
document number: 002-04498 rev. *a page 67 of 92 mb90340e series ? internal shift clock mode sck0 to sck3 2.4 v t scyc 0.8 v sot0 to sot3 0.8 v 2.4 v t shovi sin0 to sin3 v il v ih t ivsli v il v ih t slixi ? external shift clock mode sck0 to sck3 v ih v il sot0 to sot3 0.8 v 2.4 v t shove sin0 to sin3 v il v ih t ivsle v il v ih t slixe v ih v il t shsl t r t f t slsh
document number: 002-04498 rev. *a page 68 of 92 mb90340e series ? bit setting: escr:sces ? 0, eccr:scde ? 1 (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? 0 v) note: ? c l is load capacity value of pins when testing. ? t cp is internal operating clock cycle ti me (machine clock) . refer to ? clock timing ?. parameter symbol pin condition value unit min max serial clock cycle time t scyc sck0 to sck3 internal clock operation output pins are c l ? 80 pf ? 1 ttl. 5 t cp ? ns sck ? ? sot delay time t shovi sck0 to sck3, sot0 to sot3 ? 50 ? 50 ns valid sin ? sck ? t ivsli sck0 to sck3, sin0 to sin3 t cp ? 80 ? ns sck ? ? valid sin hold time t slixi sck0 to sck3, sin0 to sin3 0 ? ns sot ? sck ? delay time t sovli sck0 to sck3, sot0 to sot3 3 t cp ? 70 ? ns s ck0 to sck3 2.4 v t scyc 0.8 v s ot0 to sot3 0.8 v 2.4 v t sovli s in0 to sin3 v il v ih t ivsli v il v ih t slixi 0.8 v t shovi 0.8 v 2.4 v
document number: 002-04498 rev. *a page 69 of 92 mb90340e series ? bit setting: escr:sces ? 1, eccr:scde ? 1 (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? 0 v) note: ? c l is load capacity value of pins when testing. ? t cp is internal operating clock cycle ti me (machine clock) . refer to ? clock timing ?. parameter symbol pin condition value unit min max serial clock cycle time t scyc sck0 to sck3 internal clock operation output pins are c l ? 80 pf ? 1 ttl. 5 t cp ? ns sck ? ? sot delay time t slovi sck0 to sck3, sot0 to sot3 ? 50 ? 50 ns valid sin ? sck ? t ivshi sck0 to sck3, sin0 to sin3 t cp ? 80 ? ns sck ? ? valid sin hold time t shixi sck0 to sck3, sin0 to sin3 0 ? ns sot ? sck ? delay time t sovhi sck0 to sck3, sot0 to sot3 3 t cp ? 70 ? ns sck0 to sck3 2.4 v t scyc 2.4 v sot0 to sot3 0.8 v 2.4 v t sovhi sin0 to sin3 v il v ih t ivshi v il v ih t shixi 0.8 v t slovi 0.8 v 2.4 v
document number: 002-04498 rev. *a page 70 of 92 mb90340e series 11.4.10 trigger input timing (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? 0.0 v) parameter symbol pin condition value unit min max input pulse width t trgh t trgl int0 to int15, int0r to int15r, adtg ? 5 t cp ? ns v il v ih t trgh v il v ih t trgl int0 to int15, int0r to int15r, adtg
document number: 002-04498 rev. *a page 71 of 92 mb90340e series 11.4.11 timer related resource input timing (t a ? ? 40c to ? 105c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? 0 v) 11.4.12 timer related resource output timing (t a = ?40 ? c to +105 ? c, v cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss = 0.0 v) parameter symbol pin condition value unit min max input pulse width t tiwh tin0 to tin3, in0 to in7 ? 4 t cp ? ns t tiwl parameter symbol pin condition value unit min max clk ? ? t out change time t to tot0 to tot3, ppg0 to ppgf ? 30 ? ns v il v ih t tiwh v il v ih t tiwl tin0 to tin3, in0 to in7 clk 2.4 v 0.8 v 2.4 v t to tot0 to tot3, ppg0 to ppgf
document number: 002-04498 rev. *a page 72 of 92 mb90340e series 11.4.13 i 2 c timing (t a ? ?40 ? c to +105 ? c, v cc ? 5.0 v ? 10 ? , v ss ? 0.0 v) *1:for use at over 100 khz, set the machine clock to at least 6 mhz. *2:r,c: pull-up resistor and load capacitor of the scl and sda lines. *3:the maximum t hddat meets the requirement that it does not extend the ?l? width (t low ) of the scl signal. *4:a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat ? 250 ns must then be met. parameter symbol condition standard-mode fast-mode* 1 unit min max min max scl clock frequency f scl r ? 1.7 k ? , c ? 50 pf* 2 0 100 0 400 khz hold time (repeated) start condition sda ? ? scl ? t hdsta 4.0 ? 0.6 ?? s ?l? width of the scl clock t low 4.7 ? 1.3 ?? s ?h? width of the scl clock t high 4.0 ? 0.6 ?? s set-up time (repeated) start condition scl ? ? sda ? t susta 4.7 ? 0.6 ?? s data hold time scl ? ? sda ? ? t hddat 03.45* 3 00.9* 4 ? s data set-up time sda ? ? ? scl ? t sudat 250 ? 100 ? ns set-up time for stop condition scl ? ? sda ? t susto 4.0 ? 0.6 ?? s bus free time between a stop and start condition t bus 4.7 ? 1.3 ?? s sda scl t low t sudat t hdsta t bus t hdsta v il v il v ih v il v il v ih v ih v ih v ih v ih v ih v ih v ih v il v il v il v ih t hddat t high t susta t susto
document number: 002-04498 rev. *a page 73 of 92 mb90340e series 11.5 a/d converter (t a ? ? 40c to ? 105c, 3.0 v ? avrh ? avrl, v cc ? av cc ? 5.0 v ? 10 ? , f cp ? 24 mhz, v ss ? av ss ? 0 v) *: if the a/d convertor is not operating, a current when cpu is stopped is applicable (v cc ? av cc ? avrh ? 5.0 v) . note: : the accuracy gets worse as |avrh ? avrl| becomes smaller. parameter symbol pin value unit remarks min typ max resolution ?? ? ? 10 bit to ta l e r r o r ?? ??? 3.0 lsb nonlinearity error ?? ??? 2.5 lsb differential nonlinearity error ?? ??? 1.9 lsb zero reading voltage v ot an0 to an23 avrl ? 1.5 ? lsb avrl ? 0.5 ? lsb avrl ? 2.5 ? lsb v full scale reading voltage v fst an0 to an23 avrh ? 3.5 ? lsb avrh ? 1.5 ? lsb avrh ? 0.5 ? lsb v compare time ?? 1.0 ? 16500 ? s 4.5 v ? av cc ? 5.5 v 2.0 4.0 v ? av cc < 4.5 v sampling time ?? 0.5 ? ? ? s 4.5 v ? av cc ? 5.5 v 1.2 4.0 v ? av cc < 4.5 v analog port input current i ain an0 to an23 ? 0.3 ?? 0.3 ? a analog input voltage range v ain an0 to an23 avrl ? avrh v reference voltage range ? avrh avrl ? 2.7 ? av cc v ? avrl 0 ? avrh ? 2.7 v power supply current i a av cc ? 3.5 7.5 ma i ah av cc ?? 5 ? a* reference voltage current i r avrh ? 600 900 ? a i rh avrh ?? 5 ? a* offset between input channels ? an0 to an23 ?? 4lsb
document number: 002-04498 rev. *a page 74 of 92 mb90340e series 11.6 definition of a/d converter terms (continued) resolution : analog variation that is recognized by the a/d converter. non linearity error : the deviation between the actual conversion characteristics and a line that joins the zero-transition line ( ?00 0000 0000? ? ? ?00 0000 0001? ) to the full-scale transition line ( ?11 1111 1110? ? ? ?11 1111 1111? ) . differential linearity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. total error : difference between the actual value and the id eal value. the total error includes zero transition error, full-scale tran sition error, and linear error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error total error of digital output ?n? ? v nt ? {1 lsb ? (n ? 1) ? 0.5 lsb} 1 lsb [lsb] 1 lsb (ideal value) ? avrh ? avrl 1024 [v] v ot (ideal value) ? avrl ? 0.5 lsb [v] v fst (ideal value) ? avrh ? 1.5 lsb [v] v nt : a voltage at which the digital output transitions from (n ? 1) h to n h . n : value of the digital out put from the a/d converter
document number: 002-04498 rev. *a page 75 of 92 mb90340e series (continued) 11.7 notes on a/d converter section use the device with external circuits of th e following output impedance for analog inputs : recommended output impedance of extern al circuits are : approx. 1.5 k ? or lower (4.0 v ? av cc ? 5.5 v, sampling period ? 0.5 ? s) if an external capacitor is used, in c onsideration of the c apacitive voltage dividing effect bet ween the external capacitor and the internal on-chip capacitor, it is recomme nded that the capacitance of the external capacitor be several thousand times greater than the capacitance of th e internal capacitor. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h avrl avrh avrl avrh (n + 1) h n h (n ? 1) h (n ? 2) h v ot ( actual measurement value ) {1 lsb (n ? 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) non linearity erro r differential linearity error non linearity error of digital output n ? v nt ? {1 lsb ? (n ? 1) ? v ot } 1 lsb [lsb] differential linearity erro r of digital output n ? v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] 1 lsb ? n : value of the digital out put from the a/d converter v ot : voltage at which digita l output transits from ?000 h ? to ?001 h .? v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h .?
document number: 002-04498 rev. *a page 76 of 92 mb90340e series if the output impedance of the external ci rcuit is too high, a sampling period for an analog voltage may be insufficient. c comparator analog input r 4.5 v ? av cc ? 5.5 v : r : = 2.52 k ? , c : = 10.7 pf 4.0 v ? av cc < 4.5 v : r : = 13.6 k ? , c : = 10.7 pf a ? analog input circuit model note: : use the values in the figure only as a guideline.
document number: 002-04498 rev. *a page 77 of 92 mb90340e series 11.8 flash memory program/erase characteristics * : this value was converted from the results of evaluating the reliability of the technology (using arrhenius equation to tran slate high temperature measurements into normalized value at ? 85c) . parameter conditions value unit remarks min typ max sector erase time t a ? ? 25c v cc ? 5.0 v ? 115s excludes programming prior to erasure chip erase time ? 9 ? s excludes programming prior to erasure word (16-bit width) programming time ? 16 3600 ? s except for the over head time of the system program/erase cycle ? 10000 ?? cycle flash data retention time average t a ? ? 85c 20 ?? year *
document number: 002-04498 rev. *a page 78 of 92 mb90340e series 12. example characteristics ? mb90f346e, mb90f346es, mb90f346ce, mb90f346ces i cc ? v cc i ccl ? v cc t a ? ? 25c, external clock operation, f ? internal operation frequency t a ? ? 25c, external clock operation, f ? internal operation frequency i ccs ? v cc i ccls ? v cc t a ? ? 25c, external clock operation, f ? internal operation frequency t a ? ? 25c, external clock operation, f ? internal operation frequency i cts ? v cc i cct ? v cc t a ? ? 25c, external clock operation, f ? internal operation frequency t a ? ? 25c, external clock operation, f ? internal operation frequency i ctspll6 ? v cc i cch ? v cc t a ? ? 25c, external clock operation, f ? internal operation frequency t a ? ? 25c, stopped i cc (ma) 70 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl ( a) 100 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 90 70 8 0 i cc s (ma) 3 5 15 5 10 v cc (v) 0 20 25 3 0 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl s ( a) 50 15 5 10 v cc (v) 0 20 3 0 40 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 45 25 3 5 i ct s ( a) 400 150 50 100 v cc (v) 0 200 3 00 2.5 3 .5 4.5 5.5 6.5 f = 2 mhz 3 50 250 i cct ( a) 20 10 6 8 v cc (v) 0 12 16 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 1 8 14 4 2 i ct s pll6 (ma) 10 3 1 2 v cc (v) 0 4 8 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz 9 6 5 7 i cch ( a) 10 5 1 2 v cc (v) 0 6 8 2.5 3 .5 4.5 5.5 6.5 9 7 3 4
document number: 002-04498 rev. *a page 79 of 92 mb90340e series ? mb90f347e, mb90f347es, mb90f347ce, mb90f347ces i cc ? v cc i ccl ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ccs ? v cc i ccls ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i cts ? v cc i cct ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ctspll6 ? v cc i cch ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, stopped i cc (ma) 70 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl ( a) 100 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 90 70 8 0 i cc s (ma) 3 5 15 5 10 v cc (v) 0 20 25 3 0 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl s ( a) 50 15 5 10 v cc (v) 0 20 3 0 40 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 45 25 3 5 i ct s ( a) 400 150 50 100 v cc (v) 0 200 3 00 2.5 3 .5 4.5 5.5 6.5 f = 2 mhz 3 50 250 i cct ( a) 20 10 6 8 v cc (v) 0 12 16 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 1 8 14 4 2 i ct s pll6 (ma) 10 3 1 2 v cc (v) 0 4 8 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz 9 6 5 7 i cch ( a) 10 5 1 2 v cc (v) 0 6 8 2.5 3 .5 4.5 5.5 6.5 9 7 3 4
document number: 002-04498 rev. *a page 80 of 92 mb90340e series ? mb90f349e, mb90f349es, mb90f349ce, mb90f349ces i cc ? v cc i ccl ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ccs ? v cc i ccls ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i cts ? v cc i cct ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ctspll6 ? v cc i cch ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, stopped i cc (ma) 70 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl ( a) 100 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 90 70 8 0 i cc s (ma) 3 5 15 5 10 v cc (v) 0 20 25 3 0 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl s ( a) 50 15 5 10 v cc (v) 0 20 3 0 40 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 45 25 3 5 i ct s ( a) 400 150 50 100 v cc (v) 0 200 3 00 2.5 3 .5 4.5 5.5 6.5 f = 2 mhz 3 50 250 i cct ( a) 20 10 6 8 v cc (v) 0 12 16 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 1 8 14 4 2 i ct s pll6 (ma) 10 3 1 2 v cc (v) 0 4 8 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz 9 6 5 7 i cch ( a) 10 5 1 2 v cc (v) 0 6 8 2.5 3 .5 4.5 5.5 6.5 9 7 3 4
document number: 002-04498 rev. *a page 81 of 92 mb90340e series ? mb90f342e, mb90f342es, mb90f342ce, mb90f342ces i cc ? v cc i ccl ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ccs ? v cc i ccls ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i cts ? v cc i cct ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ctspll6 ? v cc i cch ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, stopped i cc (ma) 70 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl ( a) 100 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 90 70 8 0 i cc s (ma) 3 5 15 5 10 v cc (v) 0 20 25 3 0 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl s ( a) 50 15 5 10 v cc (v) 0 20 3 0 40 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 45 25 3 5 i ct s ( a) 400 150 50 100 v cc (v) 0 200 3 00 2.5 3 .5 4.5 5.5 6.5 f = 2 mhz 3 50 250 i cct ( a) 20 10 6 8 v cc (v) 0 12 16 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 1 8 14 4 2 i ct s pll6 (ma) 10 3 1 2 v cc (v) 0 4 8 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz 9 6 5 7 i cch ( a) 10 5 1 2 v cc (v) 0 6 8 2.5 3 .5 4.5 5.5 6.5 9 7 3 4
document number: 002-04498 rev. *a page 82 of 92 mb90340e series ? mb90f345e, mb90f345es, mb90f345ce, mb90f345ces i cc ? v cc i ccl ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ccs ? v cc i ccls ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i cts ? v cc i cct ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ctspll6 ? v cc i cch ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, stopped i cc (ma) 70 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl ( a) 100 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 90 70 8 0 i cc s (ma) 3 5 15 5 10 0 20 25 3 0 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl s ( a) 50 15 5 10 v cc (v) 0 20 3 0 40 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 45 25 3 5 i ct s ( a) 400 150 50 100 v cc (v) 0 200 3 00 2.5 3 .5 4.5 5.5 6.5 f = 2 mhz 3 50 250 i cct ( a) 20 10 6 8 v cc (v) 0 12 16 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 1 8 14 4 2 i ct s pll6 (ma) 10 3 1 2 v cc (v) 0 4 8 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz 9 6 5 7 i cch ( a) 10 5 1 2 v cc (v) 0 6 8 2.5 3 .5 4.5 5.5 6.5 9 7 3 4
document number: 002-04498 rev. *a page 83 of 92 mb90340e series ? mb90346e, mb90346es, mb90346ce, mb90346ces i cc ? v cc i ccl ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ccs ? v cc i ccls ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i cts ? v cc i cct ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ctspll6 ? v cc i cch ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, stopped i cc (ma) 70 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl ( a) 100 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 90 70 8 0 i cc s (ma) 3 5 15 5 10 v cc (v) 0 20 25 3 0 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl s ( a) 50 15 5 10 v cc (v) 0 20 3 0 40 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 45 25 3 5 i ct s ( a) 400 150 50 100 v cc (v) 0 200 3 00 2.5 3 .5 4.5 5.5 6.5 f = 2 mhz 3 50 250 i cct ( a) 20 10 6 8 v cc (v) 0 12 16 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 1 8 14 4 2 i ct s pll6 (ma) 10 3 1 2 v cc (v) 0 4 8 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz 9 6 5 7 i cch ( a) 10 5 1 2 v cc (v) 0 6 8 2.5 3 .5 4.5 5.5 6.5 9 7 3 4
document number: 002-04498 rev. *a page 84 of 92 mb90340e series ? mb90347e, mb90347es, mb90347ce, mb90347ces i cc ? v cc i ccl ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ccs ? v cc i ccls ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i cts ? v cc i cct ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, external clock operation f ? internal operation frequency i ctspll6 ? v cc i cch ? v cc t a ? ? 25c, external clock operation f ? internal operation frequency t a ? ? 25c, stopped i cc (ma) 70 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl ( a) 100 3 0 10 20 v cc (v) 0 40 50 60 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 90 70 8 0 i cc s (ma) 3 5 15 5 10 v cc (v) 0 20 25 3 0 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl s ( a) 50 15 5 10 v cc (v) 0 20 3 0 40 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 45 25 3 5 i ct s ( a) 400 150 50 100 v cc (v) 0 200 3 00 2.5 3 .5 4.5 5.5 6.5 f = 2 mhz 3 50 250 i cct ( a) 20 10 6 8 v cc (v) 0 12 16 2.5 3 .5 4.5 5.5 6.5 f = 8 khz 1 8 14 4 2 i ct s pll6 (ma) 10 3 1 2 v cc (v) 0 4 8 2.5 3 .5 4.5 5.5 6.5 f = 24 mhz 9 6 5 7 i cch ( a) 10 5 1 2 v cc (v) 0 6 8 2.5 3 .5 4.5 5.5 6.5 9 7 3 4
document number: 002-04498 rev. *a page 85 of 92 mb90340e series ? i/o characteristics (v cc ? v oh ) ? i oh v ol ? i ol t a ? ? 25c, v cc ? 4.5 v t a ? ? 25c, v cc ? 4.5 v automotive v in ? v cc cmos v in ? v cc t a ? ? 25c other than uart-sin pin and i 2 c pin t a ? ? 25c ttl v in ? v cc cmos v in ? v cc t a ? ? 25c uart-sin pin, i 2 c pin t a ? ? 25c v cc v oh (mv) 8 00 3 00 100 200 i oh (ma) 0 400 500 600 024 7 10 700 1 3 6 5 8 9 v ol (mv) 1000 3 00 100 200 i ol (ma) 0 400 500 600 900 700 8 00 024 7 10 1 3 6 5 8 9 v in (v) 5.0 1.5 0.5 1.0 v cc (v) 0.0 2.0 3 .0 3 .5 2.5 2.5 3 .5 4.5 5.5 6.5 3 .0 4.0 5.0 6.0 7.0 4.0 4.5 v iha v ila v in (v) 5.0 2.5 1.5 2.0 v cc (v) 0.0 3 .0 4.0 2.5 3 .5 4.5 5.5 6.5 4.5 3 .5 1.0 0.5 v ih s v il s 3 .0 4.0 5.0 6.0 7.0 v in (v) 2.5 0. 8 0. 3 0.5 v cc (v) 0.0 1.0 2.0 2.5 3 .5 4.5 5.5 6.5 2. 3 1.5 1. 3 1. 8 3 .0 4.0 5.0 6.0 7.0 v iht v ilt v in (v) 5.0 2.5 0.5 1.0 v cc (v) 0.0 3 .0 4.0 4.5 3 .5 1.5 2.0 2.5 3 .5 4.5 5.5 6.5 3 .0 4.0 5.0 6.0 7.0 v ih s v il s
document number: 002-04498 rev. *a page 86 of 92 mb90340e series 13. ordering information (continued) part number package remarks mb90f342epf 100-pin plastic qfp (fpt-100p-m06) mb90f342espf mb90f342cepf mb90f342cespf mb90f342epmc 100-pin plastic lqfp (fpt-100p-m20) mb90f342espmc mb90f342cepmc mb90f342cespmc mb90f345epf 100-pin plastic qfp (fpt-100p-m06) mb90f345espf mb90f345cepf mb90f345cespf mb90f345epmc 100-pin plastic lqfp (fpt-100p-m20) mb90f345espmc mb90f345cepmc mb90f345cespmc mb90f346epf 100-pin plastic qfp (fpt-100p-m06) mb90f346espf mb90f346cepf mb90f346cespf mb90f346epmc 100-pin plastic lqfp (fpt-100p-m20) mb90f346espmc mb90f346cepmc mb90f346cespmc
document number: 002-04498 rev. *a page 87 of 92 mb90340e series (continued) part number package remarks mb90f347epf 100-pin plastic qfp (fpt-100p-m06) mb90f347espf mb90f347cepf mb90f347cespf mb90f347epmc 100-pin plastic lqfp (fpt-100p-m20) mb90f347espmc mb90f347cepmc mb90f347cespmc mb90f349epf 100-pin plastic qfp (fpt-100p-m06) mb90f349espf mb90f349cepf mb90f349cespf mb90f349epmc 100-pin plastic lqfp (fpt-100p-m20) mb90f349espmc mb90f349cepmc mb90f349cespmc mb90341epf 100-pin plastic qfp (fpt-100p-m06) mb90341espf mb90341cepf mb90341cespf mb90341epmc 100-pin plastic lqfp (fpt-100p-m20) mb90341espmc mb90341cepmc mb90341cespmc mb90342epf 100-pin plastic qfp (fpt-100p-m06) mb90342espf mb90342cepf mb90342cespf mb90342epmc 100-pin plastic lqfp (fpt-100p-m20) mb90342espmc mb90342cepmc mb90342cespmc
document number: 002-04498 rev. *a page 88 of 92 mb90340e series (continued) part number package remarks mb90346epf 100-pin plastic qfp (fpt-100p-m06) mb90346espf mb90346cepf mb90346cespf mb90346epmc 100-pin plastic lqfp (fpt-100p-m20) mb90346espmc mb90346cepmc mb90346cespmc mb90347epf 100-pin plastic qfp (fpt-100p-m06) mb90347espf mb90347cepf mb90347cespf mb90347epmc 100-pin plastic lqfp (fpt-100p-m20) mb90347espmc MB90347CEPMC mb90347cespmc mb90348epf 100-pin plastic qfp (fpt-100p-m06) mb90348espf mb90348cepf mb90348cespf mb90348epmc 100-pin plastic lqfp (fpt-100p-m20) mb90348espmc mb90348cepmc mb90348cespmc mb90349epf 100-pin plastic qfp (fpt-100p-m06) mb90349espf mb90349cepf mb90349cespf mb90349epmc 100-pin plastic lqfp (fpt-100p-m20) mb90349espmc mb90349cepmc mb90349cespmc mb90v340e-101cr 299-pin ceramic pga (pga-299c-a01) for evaluation mb90v340e-102cr
document number: 002-04498 rev. *a page 89 of 92 mb90340e series 14. package dimensions 100-pin plastic lqfp lead pitch 0.50 mm package width package length 14.0 mm 14.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.65 g code (reference) p-lfqfp100-14 14-0.50 100-pin plastic lqfp (fpt-100p-m20) (fpt-100p-m20) c 2005 -2010 fujitsu semiconductor limited f100031s-c-3-5 14.00 0.10(.551 .004)sq 16.00 0.20(.630 .008)sq 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.008 .002) m 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) "a" index .059 ? .004 +.008 ? 0.10 +0.20 1.50 (mounting height) 0 ~8 0.50 0.20 (.020 .008 ) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) details of "a" part (stand off) * dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002-04498 rev. *a page 90 of 92 mb90340e series (continued) 100-pin plastic qfp lead pitch 0.65 mm package width package length 14.00 20.00 mm lead shape gullwing sealing method plastic mold mounting height 3.35 mm max code (reference) p-qfp100-14 20-0.65 100-pin plastic qfp (fpt-100p-m06) (fpt-100p-m06) c 2002-2010 fujitsu semiconductor limited f100008s-c-5-7 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 ?0.20 +.014 ?.008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 0~8 * * 14.000.20 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002-04498 rev. *a page 91 of 92 mb90340e series 15. major changes spansi i on publication number: ds07-13747-4e note: please see ?document history? about later revised information. document history page section change results ?? deleted the part numbers; mb90f343e(s), mb90f343ce(s) 51 electrical characteristics absolute maximum ratings added ?*6? in remark for ?l" level maximum output current and ?h? level maximum output current. added ?*7? in remark for ?l" level average output current and ?h? level average output current. added ?*8? in remark for ?l"level average overall output current and ?h? level average overall output current. 52 added as follows. ?*6:the maximum output current is defined as the peak value of the current of any one of the corresponding pins.? ?*7:the average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins.? ?*8:the average total output current is def ined as the value of the average current flowing over 100 ms at all of the corresponding pins.? document title: mb90340e series f2mc-16lx 16-bit microcontroller datasheet document number: 002-04498 revision ecn orig. of change submission date description of change ** ? akih 08/23/2010 migrated to cypress and assigned document number 002-04498. no change to document contents or format. *a 5221535 akih 05/04/2016 updated to cypress template
document number: 002-04498 rev. *a revised may 4,2016 page 92 of 92 mb90340e series ? cypress semiconductor corporation, 2006-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a crit ical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions cypress.com/psoc psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/support

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